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PIC16C55X(A)
EPROM-Based 8-Bit CMOS Microcontroller
Devices included in this data sheet:
Referred to collectively as PIC16C55X(A). * PIC16C554 * PIC16C558 PIC16C554A PIC16C556A PIC16C558A
Pin Diagram
PDIP, SOIC, Windowed CERDIP
RA2 RA3 RA4/T0CKI MCLR VSS RB0/INT RB1 RB2 RB3 *1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 RA1 RA0 OSC1/CLKIN OSC2/CLKOUT VDD RB7 RB6 RB5 RB4
PIC16C55X(A)
High Performance RISC CPU:
* Only 35 instructions to learn * All single-cycle instructions (200 ns), except for program branches which are two-cycle * Operating speed: - DC - 20 MHz clock input - DC - 200 ns instruction cycle Device PIC16C554 PIC16C554A PIC16C556A PIC16C558 PIC16C558A * * * * Program Memory 512 512 1K 2K 2K Data Memory 80 80 80 128 128
SSOP
RA2 RA3 RA4/T0CKI MCLR VSS VSS RB0/INT RB1 RB2 RB3 *1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 RA1 RA0 OSC1/CLKIN OSC2/CLKOUT VDD VDD RB7 RB6 RB5 RB4
PIC16C55X(A)
Interrupt capability 16 special function hardware registers 8-level deep hardware stack Direct, Indirect and Relative addressing modes
Special Microcontroller Features (cont'd)
* * * * * Programmable code protection Power saving SLEEP mode Selectable oscillator options Serial in-circuit programming (via two pins) Four user programmable ID locations
Peripheral Features:
* 13 I/O pins with individual direction control * High current sink/source for direct LED drive * Timer0: 8-bit timer/counter with 8-bit programmable prescaler
CMOS Technology:
* Low-power, high-speed CMOS EPROM technology * Fully static design * Wide operating voltage range - 2.5V to 5.5V PIC16C55X - 3.0 to 5.5V PIC16C55XA * Commercial, industrial and extended temperature range * Low power consumption - < 2.0 mA @ 5.0V, 4.0 MHz - 15 A typical @ 3.0V, 32 kHz - < 1.0 A typical standby current @ 3.0V
Special Microcontroller Features:
* Power-on Reset (POR) * Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) * Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation
(c) 1997 Microchip Technology Inc.
Preliminary
DS40143B-page 1
PIC16C55X(A)
Device Differences
Device PIC16C554 PIC16C554A PIC16C556A PIC16C558 PIC16C558A Voltage Range 2.5 - 5.5 3.0 - 5.5 3.0 - 5.5 2.5 - 5.5 3.0 - 5.5 Oscillator See Note 1 See Note 1 See Note 1 See Note 1 See Note 1 Process Technology (Microns) 0.9 0.7 0.7 0.9 0.7
Note 1: If you change from this device to another device, please verify oscillator characteristics in your application.
DS40143B-page 2
Preliminary
(c) 1997 Microchip Technology Inc.
PIC16C55X(A)
Table of Contents
1.0 General Description......................................................................................................................................................................5 2.0 PIC16C55X(A) Device Varieties...................................................................................................................................................7 3.0 Architectural Overview .................................................................................................................................................................9 4.0 Memory Organization ................................................................................................................................................................ 13 5.0 I/O Ports .................................................................................................................................................................................... 23 6.0 Timer0 Module .......................................................................................................................................................................... 29 7.0 Special Features of the CPU..................................................................................................................................................... 35 8.0 Instruction Set Summary ........................................................................................................................................................... 51 9.0 Development Support................................................................................................................................................................ 63 10.0 Electrical Specifications............................................................................................................................................................. 67 11.0 Packaging Information............................................................................................................................................................... 79 Appendix A: Enhancements............................................................................................................................................................ 87 Appendix B: Compatibility ............................................................................................................................................................... 87 INDEX .................................................................................................................................................................................................. 89 PIC16C55X(A) Product Identification System...................................................................................................................................... 95
To Our Valued Customers
We constantly strive to improve the quality of all our products and documentation. To this end, we recently converted to a new publishing software package which we believe will enhance our entire documentation process and product. As in any conversion process, information may have accidently been altered or deleted. We have spent an exceptional amount of time to ensure that these documents are correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error from the previous version of this data sheet (PIC16C55X(A) Data Sheet, Literature Number DS40143B), please use the reader response form in the back of this data sheet to inform us. We appreciate your assistance in making this a better document.
(c) 1997 Microchip Technology Inc.
Preliminary
DS40143B-page 3
PIC16C55X(A)
NOTES:
DS40143B-page 4
Preliminary
(c) 1997 Microchip Technology Inc.
PIC16C55X(A)
1.0 GENERAL DESCRIPTION
The PIC16C55X(A) are 18 and 20-Pin EPROM-based members of the versatile PIC16CXX family of low-cost, high-performance, CMOS, fully-static, 8-bit microcontrollers. All PICmicroTM microcontrollers employ an advanced RISC architecture. The PIC16C55X(A) have enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with the separate 8-bit wide data. The two-stage instruction pipeline allows all instructions to execute in a single-cycle, except for program branches (which require two cycles). A total of 35 instructions (reduced instruction set) are available. Additionally, a large register set gives some of the architectural innovations used to achieve a very high performance. PIC16C55X(A) microcontrollers typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit microcontrollers in their class. The PIC16C554(A) and PIC16C556A have 80 bytes of RAM. The PIC16C558(A) has 128 bytes of RAM. Each device has 13 I/O pins and an 8-bit timer/counter with an 8-bit programmable prescaler. PIC16C55X(A) devices have special features to reduce external components, thus reducing cost, enhancing system reliability and reducing power consumption. There are four oscillator options, of which the single pin RC oscillator provides a low-cost solution, the LP oscillator minimizes power consumption, XT is a standard crystal, and the HS is for High Speed crystals. The SLEEP (power-down) mode offers power saving. The user can wake up the chip from SLEEP through several external and internal interrupts and reset. A highly reliable Watchdog Timer with its own on-chip RC oscillator provides protection against software lock- up. A UV-erasable CERDIP-packaged version is ideal for code development while the cost-effective One-Time Programmable (OTP) version is suitable for production in any volume. Table 1-1 shows the features of the PIC16C55X(A) mid-range microcontroller families. A simplified block diagram of the PIC16C55X(A) is shown in Figure 3-1. The PIC16C55X(A) series fit perfectly in applications ranging from motor control to low-power remote sensors. The EPROM technology makes customization of application programs (detection levels, pulse generation, timers, etc.) extremely fast and convenient. The small footprint packages make this microcontroller series perfect for all applications with space limitations. Low-cost, low-power, high-performance, ease of use and I/O flexibility make the PIC16C55X(A) very versatile.
1.1
Family and Upward Compatibility
Those users familiar with the PIC16C5X family of microcontrollers will realize that this is an enhanced version of the PIC16C5X architecture. Please refer to Appendix A for a detailed list of enhancements. Code written for PIC16C5X can be easily ported to PIC16C55X(A) family of devices (Appendix B). The PIC16C55X(A) family fills the niche for users wanting to migrate up from the PIC16C5X family and not needing various peripheral features of other members of the PIC16XX mid-range microcontroller family.
1.2
Development Support
The PIC16C55X(A) family is supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a low-cost development programmer and a full-featured programmer. A "C" compiler and fuzzy logic support tools are also available.
(c) 1997 Microchip Technology Inc.
Preliminary
DS40143B-page 5
PIC16C55X(A)
TABLE 1-1: PIC16C55X(A) FAMILY OF DEVICES
PIC16C554 Clock Maximum Frequency of Oper- 20 ation (MHz) EPROM Program Memory (x14 words) Data Memory (bytes) Peripherals Timer Module(s) Interrupt Sources I/O Pins Voltage Range (Volts) Features Brown-out Reset Packages 512 80 TMR0 3 13 2.5-5.5 -- 18-pin DIP, SOIC; 20-pin SSOP PIC16C554A PIC16C556A 20 512 80 TMR0 3 13 3.0-5.5 -- 18-pin DIP, SOIC; 20-pin SSOP 20 1K 80 TMR0 3 13 3.0-5.5 -- 18-pin DIP, SOIC; 20-pin SSOP PIC16C558 20 2K 128 TMR0 3 13 2.5-5.5 -- 18-pin DIP, SOIC; 20-pin SSOP PIC16C558A 20 2K 128 TMR0 3 13 3.0-5.5 -- 18-pin DIP, SOIC; 20-pin SSOP
Memory
All PICmicroTM Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16C55X(A)Family devices use serial programming with clock pin RB6 and data pin RB7.
DS40143B-page 6
Preliminary
(c) 1997 Microchip Technology Inc.
PIC16C55X(A)
2.0 PIC16C55X(A) DEVICE VARIETIES
2.3 Quick-Turnaround-Production (QTP) Devices
A variety of frequency ranges and packaging options are available. Depending on application and production requirements the proper device option can be selected using the information in the PIC16C55X(A) Product Identification System section at the end of this data sheet. When placing orders, please use this page of the data sheet to specify the correct part number.
2.1
UV Erasable Devices
The UV erasable version, offered in CERDIP package is optimal for prototype development and pilot programs. This version can be erased and reprogrammed to any of the oscillator modes. and PROMATE(R) Microchip's PICSTART(R) programmers both support programming of the PIC16C55X(A).
Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but with all EPROM locations and configuration options already programmed by the factory. Certain code and prototype verification procedures apply before production shipments are available. Please contact your Microchip Technology sales office for more details.
2.4
Serialized Quick-Turnaround-Production (SQTPSM) Devices
2.2
One-Time-Programmable (OTP) Devices
Microchip offers a unique programming service where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential. Serial programming allows each device to have a unique number which can serve as an entry-code, password or ID number.
The availability of OTP devices is especially useful for customers who need the flexibility for frequent code updates and small volume applications. In addition to the program memory, the configuration bits must also be programmed.
(c) 1997 Microchip Technology Inc.
Preliminary
DS40143B-page 7
PIC16C55X(A)
NOTES:
DS40143B-page 8
Preliminary
(c) 1997 Microchip Technology Inc.
PIC16C55X(A)
3.0 ARCHITECTURAL OVERVIEW
The high performance of the PIC16C55X(A) family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16C55X(A) uses a Harvard architecture, in which, program and data are accessed from separate memories using separate busses. This improves bandwidth over traditional von Neumann architecture where program and data are fetched from the same memory. Separating program and data memory further allows instructions to be sized differently than 8-bit wide data words. Instruction opcodes are 14-bits wide making it possible to have all single word instructions. A 14-bit wide program memory access bus fetches a 14-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently, all instructions (35) execute in a single-cycle (200 ns @ 20 MHz) except for program branches. The PIC16C554(A) addresses 512 x 14 on-chip program memory. The PIC16C556A addresses 1K x 14 program memory. The PIC16C558(A) addresses 2K x 14 program memory. All program memory is internal. The PIC16C55X(A) can directly or indirectly address its register files or data memory. All special function registers including the program counter are mapped into the data memory. The PIC16C55X(A) have an orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of `special optimal situations' make programming with the PIC16C55X(A) simple yet efficient. In addition, the learning curve is reduced significantly. The PIC16C55X(A) devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register file. The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the working register (W register). The other operand is a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register. The W register is an 8-bit working register used for ALU operations. It is not an addressable register. Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. A simplified block diagram is shown in Figure 3-1, with a description of the device pins in Table 3-1.
(c) 1997 Microchip Technology Inc.
Preliminary
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PIC16C55X(A)
FIGURE 3-1:
Device PIC16C554 PIC16C554A PIC16C556A PIC16C558 PIC16C558A
BLOCK DIAGRAM
Program Memory 512 x 14 512 x 14 1K x 14 2K x 14 2K x 14 Data Memory (RAM) 80 x 8 80 x 8 80 x 8 128 x 8 128 x 8
EPROM Program Memory 512 x 14 to 2K x 14 Program Bus 14 Instruction reg
13 Program Counter
Data Bus
8
PORTA RA0 RA1 RA2 RA3 RA4/T0CKI PORTB
8 Level Stack (13-bit)
RAM File Registers 80 x 8 to 128 x 8 RAM Addr(1) 8
Addr MUX Direct Addr 7 8 Indirect Addr RB0/INT RB7:RB1
FSR reg STATUS reg 8 3
Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Oscillator Start-up Timer Power-on Reset Watchdog Timer
MUX
ALU 8 W reg
Timer0 MCLR VDD, VSS
Note 1: Higher order bits are from the status register.
DS40143B-page 10
Preliminary
(c) 1997 Microchip Technology Inc.
PIC16C55X(A)
TABLE 3-1:
Name
OSC1/CLKIN OSC2/CLKOUT
PIC16C55X(A) PINOUT DESCRIPTION
DIP SOIC Pin # 16 15 SSOP Pin # 18 17 I/O/P Type I O Buffer Type
Description
ST/CMOS Oscillator crystal input/external clock source input. -- Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. Master clear (reset) input/programming voltage input. This pin is an active low reset to the device. PORTA is a bi-directional I/O port.
MCLR/VPP
4
4
I/P
ST
RA0 RA1 RA2 RA3 RA4/T0CKI
17 18 1 2 3
19 20 1 2 3
I/O I/O I/O I/O I/O
ST ST ST ST ST Can be selected to be the clock input to the Timer0 timer/counter. Output is open drain type. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs.
RB0/INT RB1 RB2 RB3 RB4 RB5 RB6 RB7 VSS VDD
6 7 8 9 10 11 12 13 5 14
7 8 9 10 11 12 13 14 5,6 15,16
I/O I/O I/O I/O I/O I/O I/O I/O P P
TTL/ST(1) TTL TTL TTL TTL TTL TTL/ST -- --
(2)
RB0/INT can also be selected as an external interrupt pin.
Interrupt on change pin. Interrupt on change pin. Interrupt on change pin. Serial programming clock. Interrupt on change pin. Serial programming data. Ground reference for logic and I/O pins. Positive supply for logic and I/O pins.
TTL/ST(2)
Legend:
O = output I/O = input/output P = power -- = Not used I = Input ST = Schmitt Trigger input TTL = TTL input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. Note 2: This buffer is a Schmitt Trigger input when used in serial programming mode.
(c) 1997 Microchip Technology Inc.
Preliminary
DS40143B-page 11
PIC16C55X(A)
3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining
The clock input (OSC1/CLKIN pin) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow are shown in Figure 3-2. An "Instruction Cycle" consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO) then two cycles are required to complete the instruction (Example 3-1). A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the "Instruction Register (IR)" in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q1 OSC1 Q1 Q2 Q3 Q4 PC
PC PC+1 PC+2 Internal phase clock
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC2/CLKOUT (RC mode)
Fetch INST (PC) Execute INST (PC-1)
Fetch INST (PC+1) Execute INST (PC)
Fetch INST (PC+2) Execute INST (PC+1)
EXAMPLE 3-1:
1. MOVLW 55h 2. MOVWF PORTB 3. CALL 4. BSF SUB_1
INSTRUCTION PIPELINE FLOW
Fetch 1 Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush Fetch SUB_1 Execute SUB_1
PORTA, BIT3
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is "flushed" from the pipeline while the new instruction is being fetched and then executed.
DS40143B-page 12
Preliminary
(c) 1997 Microchip Technology Inc.
PIC16C55X(A)
4.0
4.1
MEMORY ORGANIZATION
Program Memory Organization
FIGURE 4-2:
PROGRAM MEMORY MAP AND STACK FOR THE PIC16C556A
PC<12:0>
The PIC16C55X(A) has a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 512 x 14 (0000h - 01FFh) for the PIC16C554(A), 1K x 14 (0000h - 03FFh) for the PIC16C556A and 2K x 14 (0000h - 07FFh) for the PIC16C558(A) are physically implemented. Accessing a location above these boundaries will cause a wrap-around within the first 512 x 14 space PIC16C554(A) or 1K x 14 space PIC16C556A or 2K x 14 space PIC16C558(A). The reset vector is at 0000h and the interrupt vector is at 0004h (Figure 4-1, Figure 4-2, Figure 4-3).
CALL, RETURN RETFIE, RETLW
13
Stack Level 1 Stack Level 2 Stack Level 8 Reset Vector 000h
FIGURE 4-1:
PROGRAM MEMORY MAP AND STACK FOR THE PIC16C554/PIC6C554A
PC<12:0>
Interrupt Vector
0004 0005
CALL, RETURN RETFIE, RETLW
13
On-chip Program Memory 03FFh 0400h
Stack Level 1 Stack Level 2
1FFFh Stack Level 8 Reset Vector
FIGURE 4-3:
000h
PROGRAM MEMORY MAP AND STACK FOR THE PIC16C558/PIC16C558A
PC<12:0>
CALL, RETURN RETFIE, RETLW
13
Interrupt Vector
0004 0005
Stack Level 1 Stack Level 2 Stack Level 8
On-chip Program Memory 01FFh 0200h
Reset Vector
000h
1FFFh Interrupt Vector 0004 0005
On-chip Program Memory 07FFh 0800h
1FFFh
(c) 1997 Microchip Technology Inc.
Preliminary
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PIC16C55X(A)
4.2 Data Memory Organization
4.2.1 GENERAL PURPOSE REGISTER FILE The data memory (Figure 4-4 and Figure 4-5) is partitioned into two Banks which contain the general purpose registers and the special function registers. Bank 0 is selected when the RP0 bit is cleared. Bank 1 is selected when the RP0 bit (STATUS <5>) is set. The Special Function Registers are located in the first 32 locations of each Bank. Register locations 20-6Fh (Bank0) on the PIC16C554(A)/556A and 20-7Fh (Bank0) and A0-BFh (Bank1) on the PIC16C558(A) are general purpose registers implemented as static RAM. Some special purpose registers are mapped in Bank 1. The register file is organized as 80 x 8 in the PIC16C554(A)/556A and 128 x 8 in the PIC16C558(A). Each is accessed either directly or indirectly through the File Select Register, FSR (Section 4.4).
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(c) 1997 Microchip Technology Inc.
PIC16C55X(A)
FIGURE 4-4:
File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h INDF(1) TMR0 PCL STATUS FSR PORTA PORTB INDF(1) OPTION PCL STATUS FSR TRISA TRISB
DATA MEMORY MAP FOR THE PIC16C554(A)/556A
File Address 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h
FIGURE 4-5:
File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h
DATA MEMORY MAP FOR THE PIC16C558(A)
File Address INDF(1) TMR0 PCL STATUS FSR PORTA PORTB INDF(1) OPTION PCL STATUS FSR TRISA TRISB 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h
PCLATH INTCON
PCLATH INTCON
PCLATH INTCON
PCLATH INTCON
PCON
PCON
6Fh 70h
General Purpose Register
General Purpose Register
General Purpose Register
BFh C0h
7Fh
FFh Bank 0 Bank 1
7Fh
FFh Bank 0 Bank 1
Unimplemented data memory locations, read as '0'. Note 1: Not a physical register.
Unimplemented data memory locations, read as '0'. Note 1: Not a physical register.
(c) 1997 Microchip Technology Inc.
Preliminary
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PIC16C55X(A)
4.2.2 SPECIAL FUNCTION REGISTERS The special function registers are registers used by the CPU and Peripheral functions for controlling the desired operation of the device (Table 4-1). These registers are static RAM. The special function registers can be classified into two sets (core and peripheral). The special function registers associated with the "core" functions are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature.
TABLE 4-1:
Address Name Bank 0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch INDF TMR0 PCL STATUS FSR PORTA PORTB
SPECIAL REGISTERS FOR THE PIC16C55X(A)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset Value on all other resets(1)
Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 Module's Register Program Counter's (PC) Least Significant Byte IRP(2) RP1(2) RP0 TO PD Z DC C
xxxx xxxx xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx
xxxx xxxx uuuu uuuu 0000 0000 000q quuu uuuu uuuu ---u uuuu uuuu uuuu -- -- -- ---0 0000 0000 000x -- -- --
Indirect data memory address pointer -- RB7 -- RB6 -- RB5 RA4 RB4 RA3 RB3 RA2 RB2 RA1 RB1 RA0 RB0
---x xxxx xxxx xxxx -- -- --
Unimplemented Unimplemented Unimplemented PCLATH INTCON Unimplemented -- GIE -- (3) -- T0IE Write buffer for upper 5 bits of program counter INTE RBIE T0IF INTF RBIF
---0 0000 0000 000x -- -- --
0Dh-1Eh Unimplemented 1Fh Bank 1 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh-9Eh 9Fh INDF OPTION PCL STATUS FSR TRISA TRISB Unimplemented Unimplemented Unimplemented PCLATH INTCON Unimplemented Unimplemented PCON Unimplemented Unimplemented -- -- -- -- -- -- POR -- -- GIE -- (3) -- T0IE Write buffer for upper 5 bits of program counter INTE RBIE T0IF INTF RBIF Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Unimplemented
xxxx xxxx 1111 1111 0000 0000
xxxx xxxx 1111 1111 0000 0000 000q quuu uuuu uuuu ---1 1111 1111 1111 -- -- -- ---0 0000 0000 000x -- -- ---- --u-- --
Program Counter's (PC) Least Significant Byte -- -- RP0 TO PD Z DC C
0001 1xxx xxxx xxxx
Indirect data memory address pointer -- TRISB7 -- TRISB6 -- TRISB5 TRISA4 TRISB4 TRISA3 TRISB3 TRISA2 TRISB2 TRISA1 TRISB1 TRISA0 TRISB0
---1 1111 1111 1111 -- -- -- ---0 0000 0000 000x -- -- ---- --0-- --
Legend: -- = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: Other (non power-up) resets include MCLR reset and Watchdog Timer reset during normal operation. Note 2: IRP & RPI bits are reserved, always maintain these bits clear. Note 3: Bit 6 of INTCON register is reserved for future use. Always maintain this bit as clear.
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Preliminary
(c) 1997 Microchip Technology Inc.
PIC16C55X(A)
4.2.2.1 STATUS REGISTER The STATUS register, shown in Figure 4-6, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as the destination may be different than intended. For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the status register as 000uu1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions be used to alter the STATUS register because these instructions do not affect any status bits. For other instructions, not affecting any status bits, see the "Instruction Set Summary". Note 1: The IRP and RP1 bits (STATUS<7:6>) are not used by the PIC16C55X(A) and should be programmed as '0'. Use of these bits as general purpose R/W bits is NOT recommended, since this may affect upward compatibility with future products. The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.
Note 2:
FIGURE 4-6:
STATUS REGISTER (ADDRESS 03H OR 83H)
R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit0
Reserved Reserved IRP RP1 bit7
R W -n -x
= Readable bit = Writable bit = Value at POR reset = Unknown at POR reset
bit 7:
IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh) The IRP bit is reserved on the PIC16C55X(A), always maintain this bit clear.
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) Each bank is 128 bytes. The RP1 bit is reserved on the PIC16C55X(A), always maintain this bit clear. bit 4: TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(for borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) 1 = A carry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result occurred Note: For borrow the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.
bit 3:
bit 2:
bit 1:
bit 0:
(c) 1997 Microchip Technology Inc.
Preliminary
DS40143B-page 17
PIC16C55X(A)
4.2.2.2 OPTION REGISTER The OPTION register is a readable and writable register which contains various control bits to configure the TMR0/WDT prescaler, the external RB0/INT interrupt, TMR0 and the weak pull-ups on PORTB. Note: To achieve a 1:1 prescaler assignment for TMR0, assign the prescaler to the WDT (PSA = 1).
FIGURE 4-7:
R/W-1 RBPU bit7
OPTION REGISTER (ADDRESS 81H)
R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit0
R/W-1 INTEDG
R = Readable bit W = Writable bit - n = Value at POR reset
bit 7:
RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module
bit 6:
bit 5:
bit 4:
bit 3:
bit 2-0: PS2:PS0: Prescaler Rate Select bits
Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
DS40143B-page 18
Preliminary
(c) 1997 Microchip Technology Inc.
PIC16C55X(A)
4.2.2.3 INTCON REGISTER Note: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). The INTCON register is a readable and writable register which contains the various enable and flag bits for all interrupt sources.
FIGURE 4-8:
R/W-0 GIE bit7
INTCON REGISTER (ADDRESS 0BH OR 8BH)
R/W-0 T0IE R/W-0 INTE R/W-0 RBIE R/W-0 T0IF R/W-0 INTF R/W-x RBIF bit0
Reserved --
R W -n -x
= Readable bit = Writable bit = Value at POR reset = Unknown at POR reset
bit 7:
GIE: Global Interrupt Enable bit 1 = Enables all un-masked interrupts 0 = Disables all interrupts
-- = Reserved for future use. Always maintain this bit clear.
bit 6: bit 5:
T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt T0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur RBIF: RB Port Change Interrupt Flag bit 1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
(c) 1997 Microchip Technology Inc.
Preliminary
DS40143B-page 19
PIC16C55X(A)
4.2.2.4 PCON REGISTER The PCON register contains flag bits to differentiate between a Power-on Reset, an external MCLR reset or WDT reset. See Section 7.3 and Section 7.4 for detailed reset operation.
FIGURE 4-9:
U-0 -- bit7
PCON REGISTER (ADDRESS 8Eh)
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 POR U-0 -- bit0
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7-2: Unimplemented: Read as '0' bit 1: POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = Power-on Reset occurred Unimplemented: Read as '0'
bit 0:
DS40143B-page 20
Preliminary
(c) 1997 Microchip Technology Inc.
PIC16C55X(A)
4.3 PCL and PCLATH
4.3.2 STACK The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high bits (PC<12:8>) are not directly readable or writable and come from PCLATH. On any reset, the PC is cleared. Figure 4-10 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH). The lower example in the figure shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> PCH). The PIC16C55X(A) family has an 8 level deep x 13-bit wide hardware stack (Figure 4-1, Figure 4-2 and Figure 4-3). The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). Note 1: There are no STATUS bits to indicate stack overflow or stack underflow conditions. Note 2: There are no instructions mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions, or vectoring to an interrupt address.
FIGURE 4-10: LOADING OF PC IN DIFFERENT SITUATIONS
PCH 12 PC 5 PCLATH<4:0> 8 8 7 PCL 0 Instruction with PCL as Destination ALU result
PCLATH PCH 12 PC 2 PCLATH<4:3> 11 Opcode <10:0> PCLATH 11 10 8 7 PCL 0 GOTO, CALL
4.3.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256 byte block). Refer to the application note "Implementing a Table Read" (AN556).
(c) 1997 Microchip Technology Inc.
Preliminary
DS40143B-page 21
PIC16C55X(A)
4.4 Indirect Addressing, INDF and FSR Registers
A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 4-1.
The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the file select register (FSR). Reading INDF itself indirectly will produce 00h. Writing to the INDF register indirectly results in a no-operation (although status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 4-11. However, IRP is not used in the PIC16C55X(A).
EXAMPLE 4-1:
movlw movwf clrf incf btfss goto
INDIRECT ADDRESSING
0x20 FSR INDF FSR FSR,4 NEXT ;initialize pointer ;to RAM ;clear INDF register ;inc pointer ;all done? ;no clear next ;yes continue
NEXT
CONTINUE:
FIGURE 4-11:
DIRECT/INDIRECT ADDRESSING PIC16C55X(A)
Direct Addressing Indirect Addressing
0 IRP(1) 7 FSR register 0
(1)RP1
RP0
6
from opcode
bank select
location select 00 00h 01 10 11
bank select 00h
location select
not used Data Memory
7Fh
7Fh
Bank 0
Bank 1
Bank 2
Bank 3
For memory map detail see Figure 4-4 and Figure 4-5. Note 1: The RP1 and IRP bits are reserved, always maintain these bits clear.
DS40143B-page 22
Preliminary
(c) 1997 Microchip Technology Inc.
PIC16C55X(A)
5.0
5.1
I/O PORTS
PORTA and TRISA Registers
FIGURE 5-2:
Data bus WR PORTA
BLOCK DIAGRAM OF RA4 PIN
The PIC16C55X(A) have two ports, PORTA and PORTB.
D Q Q
PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger input and an open drain output. Port RA4 is multiplexed with the T0CKI clock input. All other RA port pins have Schmitt Trigger input levels and full CMOS output drivers. All pins have data direction bits (TRIS registers) which can configure these pins as input or output. A '1' in the TRISA register puts the corresponding output driver in a hi- impedance mode. A '0' in the TRISA register puts the contents of the output latch on the selected pin(s). Reading the PORTA register reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. So a write to a port implies that the port pins are first read, then this value is modified and written to the port data latch.
Note: On reset, the TRISA register is set to all inputs.
CK
N Data Latch
D Q Q
I/O pin(1)
VSS Schmitt Trigger input buffer
WR TRISA
CK
TRISA Latch
RD TRISA
Q D EN EN
RD PORTA TMR0 clock input Note 1: I/O pin has protection diodes to VSS only.
FIGURE 5-1:
BLOCK DIAGRAM OF PORT PINS RA<3:0>
Data bus WR PortA
D
Q VDD
CK
Q
P N
Data Latch D WR TRISA Q I/O pin
CK
Q
VSS Schmitt Trigger input buffer
TRIS Latch
RD TRISA Q D
EN RD PORTA
(c) 1997 Microchip Technology Inc.
Preliminary
DS40143B-page 23
PIC16C55X(A)
TABLE 5-1:
Name
PORTA FUNCTIONS
Bit # Buffer Type Function Input/output Input/output Input/output Input/output Input/output or external clock input for TMR0. Output is open drain type.
RA0 bit0 ST RA1 bit1 ST RA2 bit2 ST RA3 bit3 ST RA4/T0CKI bit4 ST Legend: ST = Schmitt Trigger input
TABLE 5-2:
Address Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Value on All Other Resets
05h 85h
PORTA TRISA
-- --
-- --
-- --
RA4
RA3
RA2
RA1
RA0
---x xxxx ---1 1111
---u uuuu ---1 1111
TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
Legend: -- = Unimplemented locations, read as `0' Note: Note: Shaded bits are not used by PORTA.
DS40143B-page 24
Preliminary
(c) 1997 Microchip Technology Inc.
PIC16C55X(A)
5.2 PORTB and TRISB Registers
PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. A '1' in the TRISB register puts the corresponding output driver in a high impedance mode. A '0' in the TRISB register puts the contents of the output latch on the selected pin(s). Reading PORTB register reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. So a write to a port implies that the port pins are first read, then this value is modified and written to the port data latch. Each of the PORTB pins has a weak internal pull-up (200 A typical). A single control bit can turn on all the pull-ups. This is done by clearing the RBPU (OPTION<7>) bit. The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on Power-on Reset. Four of PORTB's pins, RB7:RB4, have an interrupt on change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin configured as an output is excluded from the interrupt on change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The "mismatch" outputs of RB7:RB4 are OR'ed together to generate the RBIF interrupt (flag latched in INTCON<0>). This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the interrupt in the following manner: a) b) Any read or write of PORTB. This will end the mismatch condition. Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition, and allow flag bit RBIF to be cleared. This interrupt on mismatch feature, together with software configurable pull-ups on these four pins allow easy interface to a key pad and make it possible for wake-up on key-depression. (See AN552 in the Microchip Embedded Control Handbook.)
Note: If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the RBIF interrupt flag may not get set.
The interrupt on change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt on change feature. Polling of PORTB is not recommended while using the interrupt on change feature.
FIGURE 5-4:
BLOCK DIAGRAM OF RB3:RB0 PINS
VDD weak P pull-up Data Latch D Q CK D Q CK I/O pin(1)
FIGURE 5-3:
BLOCK DIAGRAM OF RB7:RB4 PINS
VDD weak P pull-up Data Latch D Q CK TRIS Latch D Q I/O pin(1)
RBPU(2)
Data bus WR PortB
RBPU(2)
Data bus WR PortB
WR TRISB
TTL Input Buffer
WR TRISB
CK
TTL Input Buffer
RD TRISB ST Buffer RD PortB Q EN D
RD TRISB Q RD PortB Set RBIF From other RB7:RB4 pins
Latch D EN RB0/INT ST Buffer RD Port
Q EN
D
Note 1: I/O pins have diode protection to VDD and VSS. RD Port Note 2: TRISB = 1 enables weak pull-up if RBPU = '0' (OPTION<7>).
RB7:RB6 in serial programming mode
Note 1: I/O pins have diode protection to VDD and VSS. Note 2: TRISB = 1 enables weak pull-up if RBPU = '0' (OPTION<7>).
(c) 1997 Microchip Technology Inc.
Preliminary
DS40143B-page 25
PIC16C55X(A)
TABLE 5-3:
Name RB0/INT
PORTB FUNCTIONS
Bit # bit0 Buffer Type TTL/ST(1) Function
Input/output or external interrupt input. Internal software programmable weak pull-up. RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. (2) RB6 bit6 Input/output pin (with interrupt on change). Internal software TTL/ST programmable weak pull-up. Serial programming clock pin. (2) RB7 bit7 Input/output pin (with interrupt on change). Internal software TTL/ST programmable weak pull-up. Serial programming data pin. Legend: ST = Schmitt Trigger, TTL = TTL input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. Note 2: This buffer is a Schmitt Trigger input when used in serial programming mode.
TABLE 5-4:
Address Name 06h 86h 81h PORTB TRISB OPTION
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Bit 7 RB7 TRISB7 RBPU Bit 6 RB6 TRISB6 INTEDG Bit 5 RB5 Bit 4 RB4 Bit 3 RB3 Bit 2 RB2 Bit 1 RB1 Bit 0 RB0 Value on POR Value on All Other Rests
uuuu uuuu 1111 1111 1111 1111
xxxx xxxx 1111 1111 1111 1111
TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 T0CS T0SE PSA PS2 PS1 PS0
Note:
Shaded bits are not used by PORTB.
DS40143B-page 26
Preliminary
(c) 1997 Microchip Technology Inc.
PIC16C55X(A)
5.3
5.3.1
I/O Programming Considerations
BI-DIRECTIONAL I/O PORTS
EXAMPLE 5-1:
READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT
Any instruction which writes, operates internally as a read followed by a write operation. The BCF and BSF instructions, for example, read the register into the CPU, execute the bit operation and write the result back to the register. Caution must be used when these instructions are applied to a port with both inputs and outputs defined. For example, a BSF operation on bit5 of PORTB will cause all eight bits of PORTB to be read into the CPU. Then the BSF operation takes place on bit5 and PORTB is written to the output latches. If another bit of PORTB is used as a bidirectional I/O pin (e.g., bit0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the CPU and re-written to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the input mode, no problem occurs. However, if bit0 is switched into output mode later on, the content of the data latch may now be unknown. Reading the port register, reads the values of the port pins. Writing to the port register writes the value to the port latch. When using read modify write instructions (ex. BCF, BSF, etc.) on a port, the value of the port pins is read, the desired operation is done to this value, and this value is then written to the port latch. Example 5-1 shows the effect of two sequential read-modify-write instructions (ex., BCF, BSF, etc.) on an I/O port. A pin actively outputting a Low or High should not be driven from external devices at the same time in order to change the level on this pin ("wired-or", "wired-and"). The resulting high output currents may damage the chip.
; Initial PORT settings: PORTB<7:4> Inputs ; ; PORTB<3:0> Outputs ; PORTB<7:6> have external pull-up and are not ; connected to other circuitry ; ; PORT latch PORT pins ; ---------- ---------BCF BCF BSF BCF BCF PORTB, 7 PORTB, 6 STATUS,RP0 TRISB, 7 TRISB, 6 ; 01pp ; 10pp ; ; 10pp ; 10pp pppp pppp pppp pppp 11pp pppp 11pp pppp 11pp pppp 10pp pppp
; ; Note that the user may have expected the pin ; values to be 00pp pppp. The 2nd BCF caused ; RB7 to be latched as the pin value (High).
5.3.2
SUCCESSIVE OPERATIONS ON I/O PORTS
The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 5-5). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should be such to allow the pin voltage to stabilize (load dependent) before the next instruction which causes that file to be read into the CPU is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with an NOP or another instruction not accessing this I/O port.
FIGURE 5-5:
SUCCESSIVE I/O OPERATION
Q1 Q2 Q3 Q4 PC + 1 MOVF PORTB, W Read PORTB Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Note: This example shows write to PORTB followed by a read from PORTB. Note that: data setup time = (0.25 TCY - TPD) where TCY = instruction cycle and TPD = propagation delay of Q1 cycle to output valid.
Q1 Q2 Q3 Q4 PC Instruction fetched
RB7:RB0 RB <7:0>
PC MOVWF PORTB Write to PORTB
PC + 2 NOP
PC + 3 NOP
TPD Execute MOVWF PORTB
Port pin sampled here Execute MOVF PORTB, W Execute NOP
Therefore, at higher clock frequencies, a write followed by a read may be problematic.
(c) 1997 Microchip Technology Inc.
Preliminary
DS40143B-page 27
PIC16C55X(A)
NOTES:
DS40143B-page 28
Preliminary
(c) 1997 Microchip Technology Inc.
PIC16C55X(A)
6.0 TIMER0 MODULE
The Timer0 module timer/counter has the following features: * * * * * * 8-bit timer/counter Readable and writable 8-bit software programmable prescaler Internal or external clock select Interrupt on overflow from FFh to 00h Edge select for external clock bit (OPTION<4>). Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.2. The prescaler is shared between the Timer0 module and the WatchdogTimer. The prescaler assignment is controlled in software by the control bit PSA (OPTION<3>). Clearing the PSA bit will assign the prescaler to Timer0. The prescaler is not readable or writable. When the prescaler is assigned to the Timer0 module, prescale value of 1:2, 1:4, ..., 1:256 are selectable. Section 6.3 details the operation of the prescaler.
Figure 6-1 is a simplified block diagram of the Timer0 module. Timer mode is selected by clearing the T0CS bit (OPTION<5>). In timer mode, the TMR0 will increment every instruction cycle (without prescaler). If Timer0 is written, the increment is inhibited for the following two cycles (Figure 6-2 and Figure 6-3). The user can work around this by writing an adjusted value to TMR0. Counter mode is selected by setting the T0CS bit. In this mode Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the source edge (T0SE) control
6.1
TIMER0 Interrupt
Timer0 interrupt is generated when the TMR0 register timer/counter overflows from FFh to 00h. This overflow sets the T0IF bit. The interrupt can be masked by clearing the T0IE bit (INTCON<5>). The T0IF bit (INTCON<2>) must be cleared in software by the Timer0 module interrupt service routine before re-enabling this interrupt. The Timer0 interrupt cannot wake the processor from SLEEP since the timer is shut off during SLEEP. See Figure 6-4 for Timer0 interrupt timing.
FIGURE 6-1:
RA4/T0CKI pin
TIMER0 BLOCK DIAGRAM
Data bus FOSC/4 0 1 1 Programmable Prescaler 0 PSout Sync with Internal clocks (2 cycle delay) Set Flag bit T0IF on Overflow TMR0 PSout 8
T0SE PS2:PS0 T0CS Note 1: 2: PSA
Bits, T0SE, T0CS, PS2, PS1, PS0 and PSA are located in the OPTION register. The prescaler is shared with Watchdog Timer (Figure 6-6)
FIGURE 6-2:
PC (Program Counter) Instruction Fetch
TIMER0 (TMR0) TIMING: INTERNAL CLOCK/NO PRESCALER
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC-1 PC MOVWF TMR0 PC+1 MOVF TMR0,W PC+2 MOVF TMR0,W PC+3 MOVF TMR0,W PC+4 MOVF TMR0,W PC+5 MOVF TMR0,W PC+6
TMR0 Instruction Executed
T0
T0+1
T0+2
NT0
NT0
NT0
NT0+1
NT0+2
T0
Write TMR0 executed
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0 + 1
Read TMR0 reads NT0 + 2
(c) 1997 Microchip Technology Inc.
Preliminary
DS40143B-page 29
PIC16C55X(A)
FIGURE 6-3:
PC (Program Counter) Instruction Fetch TMR0 T0
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC-1 PC MOVWF TMR0 PC+1 MOVF TMR0,W PC+2 MOVF TMR0,W PC+3 MOVF TMR0,W PC+4 MOVF TMR0,W PC+5 MOVF TMR0,W PC+6
T0+1
NT0
NT0+1
Instruction Execute
Write TMR0 executed
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0 + 1
FIGURE 6-4:
TIMER0 INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1 CLKOUT(3) TMR0 timer T0IF bit (INTCON<2>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction fetched Instruction executed PC Inst (PC) Inst (PC-1) PC +1 Inst (PC+1) Dummy cycle PC +1 0004h Inst (0004h) Dummy cycle 0005h Inst (0005h) Inst (0004h) FEh 1 FFh 1 00h 01h 02h
Interrupt Latency Time
Inst (PC)
Note 1: T0IF interrupt flag is sampled here (every Q1). 2: Interrupt latency = 4Tcy, where Tcy = instruction cycle time. 3: CLKOUT is available only in RC oscillator mode.
DS40143B-page 30
Preliminary
(c) 1997 Microchip Technology Inc.
PIC16C55X(A)
6.2 Using Timer0 with External Clock
When an external clock input is used for Timer0, it must meet certain requirements. The external clock requirement is due to internal phase clock (TOSC) synchronization. Also, there is a delay in the actual incrementing of Timer0 after synchronization. 6.2.1 EXTERNAL CLOCK SYNCHRONIZATION When a prescaler is used, the external clock input is divided by the asynchronous ripple-counter type prescaler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple-counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4TOSC (and a small RC delay of 40 ns) divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement of 10 ns. Refer to parameters 40, 41 and 42 in the electrical specification of the desired device. 6.2.2 TIMER0 INCREMENT DELAY
When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks (Figure 6-5). Therefore, it is necessary for T0CKI to be high for at least 2TOSC (and a small RC delay of 20 ns) and low for at least 2TOSC (and a small RC delay of 20 ns). Refer to the electrical specification of the desired device.
Since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the TMR0 is actually incremented. Figure 6-5 shows the delay from the external clock edge to the timer incrementing.
FIGURE 6-5:
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Small pulse misses sampling
External Clock Input or Prescaler output (2)
(1) (3)
External Clock/Prescaler Output after sampling Increment Timer0 (Q4) Timer0 T0 T0 + 1 T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc). Therefore, the error in measuring the interval between two edges on Timer0 input = 4Tosc max. 2: External clock if no prescaler selected, Prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs.
(c) 1997 Microchip Technology Inc.
Preliminary
DS40143B-page 31
PIC16C55X(A)
6.3 Prescaler
The PSA and PS2:PS0 bits (OPTION<3:0>) determine the prescaler assignment and prescale ratio. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, BSF 1,x....etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the Watchdog Timer. The prescaler is not readable or writable. An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer, respectively (Figure 6-6). For simplicity, this counter is being referred to as "prescaler" throughout this data sheet. Note that there is only one prescaler available which is mutually exclusive between the Timer0 module and the Watchdog Timer. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the Watchdog Timer, and vice-versa.
FIGURE 6-6:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus 8 1 0 M U X SYNC 2 Cycles TMR0 reg
CLKOUT (=Fosc/4)
0 T0CKI pin 1 T0SE
M U X
T0CS
PSA
Set flag bit T0IF on Overflow
0 M U X
8-bit Prescaler 8 8-to-1MUX PS0 - PS2
Watchdog Timer
1
PSA 0 MUX 1 PSA
WDT Enable bit
WDT Time-out Note: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.
DS40143B-page 32
Preliminary
(c) 1997 Microchip Technology Inc.
PIC16C55X(A)
6.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control (i.e., it can be changed "on the fly" during program execution). To avoid an unintended device RESET, the following instruction sequence (Example 6-1) must be executed when changing the prescaler assignment from Timer0 to WDT. Lines 5-7 are required only if the desired postscaler rate is 1:1 (PS<2:0> = 000) or 1:2 (PS<2:0> = 001). To change prescaler from the WDT to the TMR0 module use the sequence shown in Example 6-2. This precaution must be taken even if the WDT is disabled.
EXAMPLE 6-2:
CHANGING PRESCALER (WDTTIMER0)
;Clear WDT and ;prescaler
CLRWDT BSF MOVLW STATUS, RP0 b'xxxx0xxx'
EXAMPLE 6-1:
CHANGING PRESCALER (TIMER0WDT)
;Select TMR0, new ;prescale value and ;clock source
STATUS, RP0 ;Skip if already in ; Bank 0 2.CLRWDT ;Clear WDT 3.CLRF TMR0 ;Clear TMR0 & Prescaler 4.BSF STATUS, RP0 ;Bank 1 5.MOVLW '00101111'b; ;These 3 lines (5, 6, 7) 6.MOVWF OPTION ; are required only if ; desired PS<2:0> are 7.CLRWDT ; 000 or 001 8.MOVLW '00101xxx'b ;Set Postscaler to 9.MOVWF OPTION ; desired WDT rate 10.BCF STATUS, RP0 ;Return to Bank 0
1.BCF
MOVWF BCF
OPTION STATUS, RP0
TABLE 6-1:
Address Name 01h 81h 85h TMR0 OPTION TRISA
REGISTERS ASSOCIATED WITH TIMER0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR uuuu uuuu INTE T0SE RBIE PSA T0IF PS2 INTF PS1 RBIF PS0 0000 000x 1111 1111 ---1 1111 Value on All Other Resets xxxx xxxx 0000 000x 1111 1111 ---1 1111
Timer0 module's register GIE RBPU -- + INTEDG -- T0IE T0CS --
0Bh/8Bh INTCON
TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
Legend: -- = Unimplemented locations, read as `0'. + = Reserved for future use. Note: Shaded bits are not used by TMR0 module.
(c) 1997 Microchip Technology Inc.
Preliminary
DS40143B-page 33
PIC16C55X(A)
NOTES:
DS40143B-page 34
Preliminary
(c) 1997 Microchip Technology Inc.
PIC16C55X(A)
7.0 SPECIAL FEATURES OF THE CPU
The PIC16C55X(A) has a Watchdog Timer which is controlled by configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 72 ms (nominal) on power-up only, designed to keep the part in reset while the power supply stabilizes. With these two functions on-chip, most applications need no external reset circuitry. The SLEEP mode is designed to offer a very low current power-down mode. The user can wake-up from SLEEP through external reset, Watchdog Timer wake-up or through an interrupt. Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select various options.
What sets a microcontroller apart from other processors are special circuits to deal with the needs of real time applications. The PIC16C55X(A) family has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These are: 1. 2. OSC selection Reset Power-on Reset (POR) Power-up Timer (PWRT) Oscillator Start-Up Timer (OST) Interrupts Watchdog Timer (WDT) SLEEP Code protection ID Locations In-circuit serial programmingTM
3. 4. 5. 6. 7. 8.
(c) 1997 Microchip Technology Inc.
Preliminary
DS40143B-page 35
PIC16C55X(A)
7.1 Configuration Bits
The configuration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device configurations. These bits are mapped in program memory location 2007h. The user will note that address 2007h is beyond the user program memory space. In fact, it belongs to the special test/configuration memory space (2000h - 3FFFh), which can be accessed only during programming.
FIGURE 7-1:
CP1 bit13 CP01
CONFIGURATION WORD
CP1 CP01 CP1 CP01 -- Reserved CP1 CP01 PWRTE WDTE F0SC1 F0SC0 bit0
CONFIG Address REGISTER: 2007h
bit 13-8 5-4:
CP<1:0>: Code protection bits(1)
11 = Code protection off 10 = Upper half of program memory code protected 01 = Upper 3/4th of program memory code protected 00 = All memory is code protected Unimplemented: Read as '1' Reserved: Do not use PWRTE: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator
bit 7: bit 6: bit 3:
bit 2:
bit 1-0:
Note 1: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
DS40143B-page 36
Preliminary
(c) 1997 Microchip Technology Inc.
PIC16C55X(A)
7.2
7.2.1
Oscillator Configurations
OSCILLATOR TYPES
TABLE 7-1:
CAPACITOR SELECTION FOR CERAMIC RESONATORS (PRELIMINARY)
The PIC16C55X(A) can be operated in four different oscillator options. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: * * * * LP XT HS RC Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator Resistor/Capacitor CRYSTAL OSCILLATOR / CERAMIC RESONATORS
Ranges Characterized: Mode XT Freq 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz OSC1(C1) 22 - 100 pF 15 - 68 pF 15 - 68 pF 10 - 68 pF 10 - 22 pF OSC2(C2) 22 - 100 pF 15 - 68 pF 15 - 68 pF 10 - 68 pF 10 - 22 pF
HS
7.2.2
In XT, LP or HS modes a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation (Figure 7-2). The PIC16C55X(A) oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in XT, LP or HS modes, the device can have an external clock source to drive the OSC1 pin (Figure 7-3).
Higher capacitance increases the stability of the oscillator but also increases the start-up time. These values are for design guidance only. Since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components. Resonators to be Characterized: 455 kHz Panasonic EFO-A455K04B 0.3% 2.0 MHz Murata Erie CSA2.00MG 0.5% 4.0 MHz Murata Erie CSA4.00MG 0.5% 8.0 MHz Murata Erie CSA8.00MT 0.5% 16.0 MHz Murata Erie CSA16.00MX 0.5% All resonators used did not have built-in capacitors.
FIGURE 7-2:
CRYSTAL OPERATION (OR CERAMIC RESONATOR) (HS, XT OR LP OSC CONFIGURATION)
OSC1 To internal logic XTAL OSC2 RS
TABLE 7-2:
CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR (PRELIMINARY)
Freq OSC1(C1) 68 - 100 pF 15 - 30 pF 68 - 150 pF 15 - 30 pF 15 - 30 pF 15 - 30 pF 15 - 30 pF 15 - 30 pF OSC2(C2) 68 - 100 pF 15 - 30 pF 150 - 200 pF 15 - 30 pF 15 - 30 pF 15 - 30 pF 15 - 30 pF 15 - 30 pF
Mode LP
RF SLEEP
C1
32 kHz 200 kHz 100 kHz 2 MHz 4 MHz 8 MHz 10 MHz 20 MHz
XT
PIC16C55X(A)
C2
see Note
See Table 7-1 and Table 7-2 for recommended values of C1 and C2. Note: A series resistor may be required for AT strip cut crystals.
HS
FIGURE 7-3:
EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION)
Higher capacitance increases the stability of the oscillator but also increases the start-up time. These values are for design guidance only. Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low drive level specification. Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. Crystals to be Characterized: 32.768 kHz 100 kHz 200 kHz 2.0 MHz 4.0 MHz 10.0 MHz 20.0 MHz Epson C-001R32.768K-A Epson C-2 100.00 KC-P STD XTL 200.000 kHz ECS ECS-20-S-2 ECS ECS-40-S-4 ECS ECS-100-S-4 ECS ECS-200-S-4 20 PPM 20 PPM 20 PPM 50 PPM 50 PPM 50 PPM 50 PPM
Clock from ext. system Open
OSC1 PIC16C55X(A) OSC2
(c) 1997 Microchip Technology Inc.
Preliminary
DS40143B-page 37
PIC16C55X(A)
7.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT 7.2.4 RC OSCILLATOR For timing insensitive applications the "RC" device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (Rext) and capacitor (Cext) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low Cext values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 7-6 shows how the R/C combination is connected to the PIC16C55X. For Rext values below 2.2 k, the oscillator operation may become unstable, or stop completely. For very high Rext values (e.g., 1 M), the oscillator becomes sensitive to noise, humidity and leakage. Thus, we recommend to keep Rext between 3 k and 100 k. Although the oscillator will operate with no external capacitor (Cext = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package lead frame capacitance. The oscillator frequency, divided by 4, is available on the OSC2/CLKOUT pin, and can be used for test purposes or to synchronize other logic (Figure 3-2 for waveform).
Either a pre-packaged oscillator can be used or a simple oscillator circuit with TTL gates can be built. Prepackaged oscillators provide a wide operating range and better stability. A well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used; one with series resonance, or one with parallel resonance. Figure 7-4 shows implementation of a parallel resonant oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04 inverter performs the 180 phase shift that a parallel oscillator requires. The 4.7 k resistor provides the negative feedback for stability. The 10 k potentiometers bias the 74AS04 in the linear region. This could be used for external oscillator designs.
FIGURE 7-4:
EXTERNAL PARALLEL RESONANT CRYSTAL OSCILLATOR CIRCUIT
To other Devices
+5V 10k 4.7k 74AS04 74AS04 CLKIN PIC16C55X(A)
10k XTAL 10k
FIGURE 7-6:
VDD
RC OSCILLATOR MODE
20 pF
20 pF
PIC16C55X(A) Rext OSC1 Internal Clock Cext VDD Fosc/4 OSC2/CLKOUT
Figure 7-5 shows a series resonant oscillator circuit. This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a 180 phase shift in a series resonant oscillator circuit. The 330 resistors provide the negative feedback to bias the inverters in their linear region.
FIGURE 7-5:
EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT
To other Devices 74AS04 CLKIN
330 74AS04 0.1 F
330 74AS04
PIC16C55X(A)
XTAL
DS40143B-page 38
Preliminary
(c) 1997 Microchip Technology Inc.
PIC16C55X(A)
7.3 Reset
The PIC16C55X(A) differentiates between various kinds of reset: a) b) c) d) e) Power-on reset (POR) MCLR reset during normal operation MCLR reset during SLEEP WDT reset (normal operation) WDT wake-up (SLEEP) on MCLR reset during SLEEP. They are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. TO and PD bits are set or cleared differently in different reset situations as indicated in Table 7-4. These bits are used in software to determine the nature of the reset. See Table 7-6 for a full description of reset states of all registers. A simplified block diagram of the on-chip reset circuit is shown in Figure 7-7. The MCLR reset path has a noise filter to detect and ignore small pulses. See Table 10-4 for pulse width specification.
Some registers are not affected in any reset condition; their status is unknown on POR and unchanged in any other reset. Most other registers are reset to a "reset state" on Power-on reset, on MCLR or WDT reset and
FIGURE 7-7:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External Reset
MCLR/ VPP Pin WDT Module VDD rise detect VDD
SLEEP WDT Time-out Reset Power-on Reset S
OST/PWRT OST 10-bit Ripple-counter OSC1/ CLKIN Pin On-chip(1) RC OSC R Q Chip_Reset
PWRT 10-bit Ripple-counter
Enable PWRT Enable OST
See Table 7-3 for time-out situations.
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
(c) 1997 Microchip Technology Inc.
Preliminary
DS40143B-page 39
PIC16C55X(A)
7.4 Power-on Reset (POR), Power-up Timer (PWRT), Oscillator Start-up Timer (OST)
POWER-ON RESET (POR) 7.4.3 OSCILLATOR START-UP TIMER (OST) The Oscillator Start-Up Timer (OST) provides a 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over. This ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP and HS modes and only on power-on reset or wake-up from SLEEP. 7.4.4 TIME-OUT SEQUENCE
7.4.1
A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1.6 V - 1.8 V). To take advantage of the POR, just tie the MCLR pin directly (or through a resistor) to VDD. This will eliminate external RC components usually needed to create Power-on Reset. A maximum rise time for VDD is required. See Electrical Specifications for details. The POR circuit does not produce internal reset when VDD declines. When the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in reset until the operating conditions are met. For additional information, refer to Application Note AN607 "Power-up Trouble Shooting". 7.4.2 POWER-UP TIMER (PWRT)
On power-up, the time-out sequence is as follows: First PWRT time-out is invoked after POR has expired, then OST is activated. The total time-out will vary based on oscillator configuration and PWRTE bit status. For example, in RC mode with PWRTE bit erased (PWRT disabled), there will be no time-out at all. Figure 7-8, Figure 7-9 and Figure 7-10 depict time-out sequences. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Then bringing MCLR high will begin execution immediately (see Figure 7-9). This is useful for testing purposes or to synchronize more than one PIC16C55X device operating in parallel. Table 7-5 shows the reset conditions for some special registers, while Table 7-6 shows the reset conditions for all the registers.
The Power-up Timer provides a fixed 72 ms (nominal) time-out on power-up only, from POR. The Power-up Timer operates on an internal RC oscillator. The chip is kept in reset as long as PWRT is active. The PWRT delay allows the VDD to rise to an acceptable level. A configuration bit, PWRTE can disable (if set) or enable (if cleared or programmed) the Power-up Timer. The Power-Up Time delay will vary from chip to chip and due to VDD, temperature and process variation. See DC parameters for details.
DS40143B-page 40
Preliminary
(c) 1997 Microchip Technology Inc.
PIC16C55X(A)
7.4.5 POWER CONTROL/STATUS REGISTER (PCON)
Bit1 is POR (Power-on-reset). It is a `0' on power-on-reset and unaffected otherwise. The user must write a `1' to this bit following a power-on-reset. On a subsequent reset if POR is `0', it will indicate that a power-on-reset must have occurred (VDD may have gone too low).
TABLE 7-3:
TIME-OUT IN VARIOUS SITUATIONS
Power-up Wake-up from SLEEP 1024 TOSC --
Oscillator Configuration PWRTE = 0 XT, HS, LP RC 72 ms + 1024 TOSC 72 ms PWRTE = 1 1024 TOSC --
TABLE 7-4:
POR
STATUS BITS AND THEIR SIGNIFICANCE
TO PD
0 0 0 1 1 1 1
1 0 X 0 0 1 1
1 X 0 1 0 1 0
Power-on-reset Illegal, TO is set on POR Illegal, PD is set on POR WDT Reset WDT Wake-up MCLR reset during normal operation MCLR reset during SLEEP
(c) 1997 Microchip Technology Inc.
Preliminary
DS40143B-page 41
PIC16C55X(A)
TABLE 7-5:
Condition Power-on Reset MCLR reset during normal operation MCLR reset during SLEEP WDT reset WDT Wake-up Interrupt Wake-up from SLEEP
INITIALIZATION CONDITION FOR SPECIAL REGISTERS
Program Counter 000h 000h 000h 000h PC + 1 PC + 1(1) STATUS Register PCON Register
0001 1xxx 0001 1uuu 0001 0uuu 0000 1uuu uuu0 0uuu uuu1 0uuu
---- --0---- --u---- --u---- --u---- --u---- --u-
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as `0'. Note 1: When the wake-up is due to an interrupt and global enable bit, GIE is set, the PC is loaded with the interrupt vector (0004h) after execution of PC+1.
TABLE 7-6:
INITIALIZATION CONDITION FOR REGISTERS
* MCLR Reset during normal operation * MCLR Reset during SLEEP * WDT Reset
Register W INDF TMR0 PCL STATUS FSR PORTA PORTB PCLATH INTCON OPTION TRISA TRISB PCON
Address 00h 01h 02h 03h 04h 05h 06h 0Ah 0Bh 81h 85h 86h 8Eh
Power-on Reset
* Wake up from SLEEP through interrupt * Wake up from SLEEP through WDT time-out
xxxx xxxx xxxx xxxx 0000 0000 0001 1xxx xxxx ---x xxxx ---0 0000 1111 ---1 1111 ---xxxx xxxx xxxx 0000 000x 1111 1111 1111 --0-
uuuu uuuu uuuu uuuu 0000 0000 000q uuuu ---u uuuu ---0 0000 quuu(3) uuuu uuuu uuuu 0000 000x
uuuu uuuu uuuu uuuu PC + 1(2) uuuq uuuu ---u uuuu ---u uuuu uuuu ---u uuuu ---quuu(3) uuuu uuuu uuuu uuuu uuuu(1) uuuu uuuu uuuu --u-
1111 1111 ---1 1111 1111 1111 ---- --u-
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as `0',q = value depends on condition.
Note 1: One or more bits in INTCON will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 7-5 for reset value for specific condition.
DS40143B-page 42
Preliminary
(c) 1997 Microchip Technology Inc.
PIC16C55X(A)
FIGURE 7-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 7-9:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 7-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): CASE 3
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
(c) 1997 Microchip Technology Inc.
Preliminary
DS40143B-page 43
PIC16C55X(A)
FIGURE 7-11: EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP)
VDD VDD
D
R R1 MCLR C
PIC16C55X(A)
Note 1: External power-on reset circuit is required only if VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: < 40 k is recommended to make sure that voltage drop across R does not violate the device's electrical specification. 3: R1 = 100 to 1 k will limit any current flowing into MCLR from external capacitor C in the event of MCLR/VPP pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS).
DS40143B-page 44
Preliminary
(c) 1997 Microchip Technology Inc.
PIC16C55X(A)
7.5 Interrupts
The PIC16C55X(A) has 3 sources of interrupt: * External interrupt RB0/INT * TMR0 overflow interrupt * PortB change interrupts (pins RB7:RB4) The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. A global interrupt enable bit, GIE (INTCON<7>) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. Individual interrupts can be disabled through their corresponding enable bits in INTCON register. GIE is cleared on reset. The "return from interrupt" instruction, RETFIE, exits the interrupt routine as well as sets the GIE bit, which re-enables RB0/INT interrupts. The INT pin interrupt, the RB port change interrupt and the TMR0 overflow interrupt flags are contained in the INTCON register. When an interrupt is responded to, the GIE is cleared to disable any further interrupt, the return address is pushed into the stack and the PC is loaded with 0004h. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid RB0/INT recursive interrupts. For external interrupt events, such as the INT pin or PORTB change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends when the interrupt event occurs (Figure 7-13). The latency is the same for one or two cycle instructions. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid multiple interrupt requests. Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit. Note 1: Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit. When an instruction that clears the GIE bit is executed, any interrupts that were pending for execution in the next cycle are ignored. The CPU will execute a NOP in the cycle immediately following the instruction which clears the GIE bit. The interrupts which were ignored are still pending to be serviced when the GIE bit is set again.
2:
FIGURE 7-12: INTERRUPT LOGIC
T0IF T0IE INTF INTE RBIF RBIE Wake-up (If in SLEEP mode)
Interrupt to CPU
GIE
(c) 1997 Microchip Technology Inc.
Preliminary
DS40143B-page 45
PIC16C55X(A)
7.5.1 RB0/INT INTERRUPT 7.5.2 TMR0 INTERRUPT An external interrupt on RB0/INT pin is edge triggered: either rising if INTEDG bit (OPTION<6>) is set, or falling if INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, the INTF bit (INTCON<1>) is set. This interrupt can be disabled by clearing the INTE control bit (INTCON<4>). The INTF bit must be cleared in software in the interrupt service routine before re-enabling this interrupt. The RB0/INT interrupt can wake-up the processor from SLEEP, if the INTE bit was set prior to going into SLEEP. The status of the GIE bit decides whether or not the processor branches to the interrupt vector following wake-up. See Section 7.8 for details on SLEEP and Figure 7-16 for timing of wake-up from SLEEP through RB0/INT interrupt. An overflow (FFh 00h) in the TMR0 register will set the T0IF (INTCON<2>) bit. The interrupt can be enabled/disabled by setting/clearing T0IE (INTCON<5>) bit. For operation of the Timer0 module, see Section 6.0. 7.5.3 PORTB INTERRUPT
An input change on PORTB <7:4> sets the RBIF (INTCON<0>) bit. The interrupt can be enabled/disabled by setting/clearing the RBIE (INTCON<4>) bit. For operation of PORTB (Section 5.2). Note: If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the RBIF interrupt flag may get set.
FIGURE 7-13: INT PIN INTERRUPT TIMING
Q1 OSC1 CLKOUT 3 INT pin INTF flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction fetched Instruction executed
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
4 1 5 Interrupt Latency 2
1
PC Inst (PC) Inst (PC-1)
PC+1 Inst (PC+1) Inst (PC)
PC+1 -- Dummy Cycle
0004h Inst (0004h) Dummy Cycle
0005h Inst (0005h) Inst (0004h)
Note 1: INTF flag is sampled here (every Q1). 2: Interrupt latency = 3-4 Tcy where Tcy = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT is available only in RC oscillator mode. 4: For minimum width of INT pulse, refer to AC specs. 5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
DS40143B-page 46
Preliminary
(c) 1997 Microchip Technology Inc.
PIC16C55X(A)
7.6 Context Saving During Interrupts 7.7 Watchdog Timer (WDT)
During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt, e.g. W register and STATUS register. This will have to be implemented in software. Example 7-1 stores and restores the STATUS and W registers. The user register, W_TEMP, must be defined in both banks and must be defined at the same offset from the bank base address (i.e., W_TEMP is defined at 0x20 in Bank 0 and it must also be defined at 0xA0 in Bank 1). The user register, STATUS_TEMP, must be defined in Bank 0. The Example 7-1: Stores the W register Stores the STATUS register in Bank 0 Executes the ISR code Restores the STATUS (and bank select bit register) * Restores the W register * * * * The watchdog timer is a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the CLKIN pin. That means that the WDT will run, even if the clock on the OSC1 and OSC2 pins of the device has been stopped, for example, by execution of a SLEEP instruction. During normal operation, a WDT time-out generates a device RESET. If the device is in SLEEP mode, a WDT time-out causes the device to wake-up and continue with normal operation. The WDT can be permanently disabled by programming the configuration bit WDTE as clear (Section 7.1). 7.7.1 WDT PERIOD
EXAMPLE 7-1:
MOVWF SWAPF BCF MOVWF : : : SWAPF (ISR) W_TEMP STATUS,W STATUS,RP0
SAVING THE STATUS AND W REGISTERS IN RAM
;copy W to temp register, ;could be in either bank ;swap status to be saved into W ;change to bank 0 regardless ;of current bank ;save status to bank 0 ;register
The WDT has a nominal time-out period of 18 ms, (with no prescaler). The time-out periods vary with temperature, VDD and process variations from part to part (see DC specs). If longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT under software control by writing to the OPTION register. Thus, time-out periods up to 2.3 seconds can be realized. The CLRWDT and SLEEP instructions clear the WDT and the postscaler, if assigned to the WDT, and prevent it from timing out and generating a device RESET. The TO bit in the STATUS register will be cleared upon a Watchdog Timer time-out. 7.7.2 WDT PROGRAMMING CONSIDERATIONS
STATUS_TEMP
STATUS_TEMP,W
;swap STATUS_TEMP register ;into W, sets bank to original ;state ;move W into STATUS register ;swap W_TEMP ;swap W_TEMP into W
MOVWF SWAPF SWAPF
STATUS W_TEMP,F W_TEMP,W
It should also be taken in account that under worst case conditions (VDD = Min., Temperature = Max., max. WDT prescaler) it may take several seconds before a WDT time-out occurs.
(c) 1997 Microchip Technology Inc.
Preliminary
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PIC16C55X(A)
FIGURE 7-14: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source (Figure 6-6)
0 Watchdog Timer
*
1
M U X
Postscaler 8 8 - to -1 MUX PS<2:0>
WDT Enable Bit
PSA
*
0 MUX 1
To TMR0 (Figure 6-6)
PSA
WDT Time-out
Note: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.
FIGURE 7-15: SUMMARY OF WATCHDOG TIMER REGISTERS
Address 2007h 81h Name Config. bits OPTION Bit 7 -- RBPU Bit 6 + INTEDG Bit 5 CP1 T0CS Bit 4 CP0 T0SE Bit 3 PWRTE PSA Bit 2 WDTE PS2 Bit 1 FOSC1 PS1 Bit 0 FOSC0 PS0
Legend: Shaded cells are not used by the Watchdog Timer. -- = Unimplemented location, read as `0'. + = Reserved for future use.
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PIC16C55X(A)
7.8 Power-Down Mode (SLEEP)
The Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit in the STATUS register is cleared, the TO bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had, before SLEEP was executed (driving high, low, or hi-impedance). For lowest current consumption in this mode, all I/O pins should be either at VDD, or VSS, with no external circuitry drawing current from the I/O pin. I/O pins that are hi-impedance inputs should be pulled high or low externally to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on chip pull-ups on PORTB should be considered. The MCLR pin must be at a logic high level (VIHMC). Note: It should be noted that a RESET generated by a WDT time-out does not drive MCLR pin low. WAKE-UP FROM SLEEP The first event will cause a device reset. The two latter events are considered a continuation of program execution. The TO and PD bits in the STATUS register can be used to determine the cause of device reset. PD bit, which is set on power-up is cleared when SLEEP is invoked. TO bit is cleared if WDT Wake-up occurred. When the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction and then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have an NOP after the SLEEP instruction. Note: If the global interrupts are disabled (GIE is cleared), but any interrupt source has both its interrupt enable bit and the corresponding interrupt flag bits set, the device will immediately wakeup from sleep. The sleep instruction is completely executed. The WDT is cleared when the device wakes-up from sleep, regardless of the source of wake-up.
7.8.1
The device can wake-up from SLEEP through one of the following events: 1. 2. 3. External reset input on MCLR pin Watchdog Timer Wake-up (if WDT was enabled) Interrupt from RB0/INT pin or RB Port change
FIGURE 7-16: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 OSC1 CLKOUT(4) INT pin INTF flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction fetched Instruction executed PC Inst(PC) = SLEEP Inst(PC - 1) PC+1 Inst(PC + 1) SLEEP PC+2 PC+2 Inst(PC + 2) Inst(PC + 1) Dummy cycle PC + 2 0004h Inst(0004h) Dummy cycle 0005h Inst(0005h) Inst(0004h) Processor in SLEEP Interrupt Latency (Note 2) TOST(2) Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Note 1: 2: 3: 4:
XT, HS or LP oscillator mode assumed. TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode. GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line. CLKOUT is not available in these osc modes, but shown here for timing reference.
(c) 1997 Microchip Technology Inc.
Preliminary
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PIC16C55X(A)
7.9 Code Protection 7.11 In-Circuit Serial ProgrammingTM
If the code protection bit(s) have not been programmed, the on-chip program memory can be read out for verification purposes. Note: Microchip does not recommend code protecting windowed devices. The PIC16C55X(A) microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. The device is placed into a program/verify mode by holding the RB6 and RB7 pins low while raising the MCLR (VPP) pin from VIL to VIHH (see programming specification). RB6 becomes the programming clock and RB7 becomes the programming data. Both RB6 and RB7 are Schmitt Trigger inputs in this mode. After reset, to place the device into programming/verify mode, the program counter (PC) is at location 00h. A 6-bit command is then supplied to the device. Depending on the command, 14-bits of program data are then supplied to or from the device, depending if the command was a load or a read. For complete details of serial programming, please refer to the PIC16C6X/7X Programming Specifications (Literature #DS30228). A typical in-circuit serial programming connection is shown in Figure 7-17.
7.10
ID Locations
Four memory locations (2000h-2003h) are designated as ID locations where the user can store checksum or other code-identification numbers. These locations are not accessible during normal execution but are readable and writable during program/verify. Only the least significant 4 bits of the ID locations are used.
FIGURE 7-17: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION
To Normal Connections PIC16C55X(A) VDD VSS MCLR/VPP RB6 RB7 VDD To Normal Connections
External Connector Signals +5V 0V VPP CLK Data I/O
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PIC16C55X(A)
8.0 INSTRUCTION SET SUMMARY
Each PIC16C55X(A) instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16C55X(A) instruction set summary in Table 8-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 8-1 shows the opcode field descriptions. For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If 'd' is zero, the result is placed in the W register. If 'd' is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' represents the number of the file in which the bit is located. For literal and control operations, 'k' represents an eight or eleven bit constant or literal value. The instruction set is highly orthogonal and is grouped into three basic categories: * Byte-oriented operations * Bit-oriented operations * Literal and control operations All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. Table 8-1 lists the instructions recognized by the MPASM assembler. Figure 8-1 shows the three general formats that the instructions can have. Note: To maintain upward compatibility with future PICmicroTM products, do not use the OPTION and TRIS instructions.
TABLE 8-1:
Field
f W b k x
OPCODE FIELD DESCRIPTIONS
Description
All examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit.
Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Don't care location (= 0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. d Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1 label Label name TOS Top of Stack PC Program Counter
PCLATH Program Counter High Latch
FIGURE 8-1:
GENERAL FORMAT FOR INSTRUCTIONS
0
Byte-oriented file register operations 13 876 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 76 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE k = 8-bit immediate value CALL and GOTO instructions only 13 11 OPCODE 10 k (literal) 8 7 k (literal)
0
GIE WDT TO PD dest []
Global Interrupt Enable bit Watchdog Timer/Counter Time-out bit Power-down bit Destination either the W register or the specified register file location Options Contents Assigned to Register bit field In the set of User defined term (font is courier)
0
() <> italics
0
k = 11-bit immediate value
(c) 1997 Microchip Technology Inc.
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PIC16C55X(A)
TABLE 8-2:
Mnemonic, Operands
PIC16C55X(A) INSTRUCTION SET
Description Cycles MSb 14-Bit Opcode LSb Status Affected Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff C,DC,Z Z Z Z Z Z Z Z Z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2
C C C,DC,Z Z
1,2 1,2 1,2 1,2 1,2
BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS f, b f, b f, b f, b Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3
LITERAL AND CONTROL OPERATIONS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW k k k k k k k k k Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into standby mode Subtract W from literal Exclusive OR literal with W 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk C,DC,Z Z TO,PD Z
TO,PD C,DC,Z Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 Module. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.
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(c) 1997 Microchip Technology Inc.
PIC16C55X(A)
8.1
ADDLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Instruction Descriptions
Add Literal and W [ label ] ADDLW 0 k 255 (W) + k (W) C, DC, Z
11 111x kkkk kkkk The contents of the W register are added to the eight bit literal 'k' and the result is placed in the W register.
ANDLW k Syntax: Operands: Operation: Status Affected: Encoding: Description:
AND Literal with W [ label ] ANDLW 0 k 255 (W) .AND. (k) (W) Z
11 1001 kkkk kkkk The contents of W register are AND'ed with the eight bit literal 'k'. The result is placed in the W register.
k
Words: Cycles: Example
1 1
ADDLW 0x15 W W = = 0x10 0x25
Words: Cycles: Example
1 1
ANDLW W W 0x5F = = 0xA3 0x03
Before Instruction After Instruction
Before Instruction After Instruction
ADDWF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Add W and f [ label ] ADDWF 0 f 127 d [0,1] (W) + (f) (dest) C, DC, Z
00 0111 dfff ffff Add the contents of the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
ANDWF f,d Syntax: Operands: Operation: Status Affected: Encoding: Description:
AND W with f [ label ] ANDWF 0 f 127 d [0,1] (W) .AND. (f) (dest) Z
00 0101 dfff ffff AND the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
f,d
Words: Cycles: Example
1 1
ADDWF FSR, 0 W= FSR = 0x17 0xC2 0xD9 0xC2
Words: Cycles: Example
1 1
ANDWF FSR, 1 W= FSR = 0x17 0xC2 0x17 0x02
Before Instruction
Before Instruction
After Instruction
W= FSR =
After Instruction
W= FSR =
(c) 1997 Microchip Technology Inc.
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PIC16C55X(A)
BCF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1
BCF FLAG_REG, 7 FLAG_REG = 0xC7
Bit Clear f [ label ] BCF 0 f 127 0b7 0 (f) None
01 00bb bfff ffff Bit 'b' in register 'f' is cleared.
BTFSC f,b Syntax: Operands: Operation: Status Affected: Encoding: Description:
Bit Test, Skip if Clear [ label ] BTFSC f,b 0 f 127 0b7 skip if (f) = 0 None
01 10bb bfff ffff If bit 'b' in register 'f' is '0' then the next instruction is skipped. If bit 'b' is '0' then the next instruction fetched during the current instruction execution is discarded, and a NOP is executed instead, making this a two-cycle instruction.
Before Instruction After Instruction
FLAG_REG = 0x47
Words: Cycles: Example
1 1(2)
HERE FALSE TRUE BTFSC GOTO * * * PC = FLAG,1 PROCESS_CODE
Before Instruction
address HERE
After Instruction
if FLAG<1> = 0, PC = address TRUE if FLAG<1>=1, PC = address FALSE
BSF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example
Bit Set f [ label ] BSF 0 f 127 0b7 1 (f) None
01 01bb bfff ffff Bit 'b' in register 'f' is set.
f,b
1 1
BSF FLAG_REG, 7
Before Instruction
FLAG_REG = 0x0A
After Instruction
FLAG_REG = 0x8A
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PIC16C55X(A)
BTFSS Syntax: Operands: Operation: Status Affected: Encoding: Description: Bit Test f, Skip if Set [ label ] BTFSS f,b 0 f 127 0b<7 skip if (f) = 1 None
01 11bb bfff ffff If bit 'b' in register 'f' is '1' then the next instruction is skipped. If bit 'b' is '1', then the next instruction fetched during the current instruction execution, is discarded and a NOP is executed instead, making this a two-cycle instruction.
CLRF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example
Clear f [ label ] CLRF 0 f 127 00h (f) 1Z Z
00 0001 1fff ffff The contents of register 'f' are cleared and the Z bit is set.
f
1 1
CLRF FLAG_REG FLAG_REG = = = 0x5A 0x00 1
Words: Cycles: Example
1 1(2)
HERE FALSE TRUE BTFSC GOTO * * * PC = FLAG,1 PROCESS_CODE
Before Instruction After Instruction
FLAG_REG Z
Before Instruction
address HERE
After Instruction
if FLAG<1> = 0, PC = address FALSE if FLAG<1> = 1, PC = address TRUE
CALL Syntax: Operands: Operation:
Call Subroutine [ label ] CALL k 0 k 2047 (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> None
10 0kkk kkkk kkkk Call Subroutine. First, return address (PC+1) is pushed onto the stack. The eleven bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two-cycle instruction.
CLRW Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example
Clear W [ label ] CLRW None 00h (W) 1Z Z
00 0001 0xxx xxxx W register is cleared. Zero bit (Z) is set.
Status Affected: Encoding: Description:
1 1
CLRW
Words: Cycles: Example
1 2
HERE CALL THERE
Before Instruction
W W Z = = = 0x5A 0x00 1
After Instruction
Before Instruction
PC = Address HERE
After Instruction
PC = Address THERE TOS = Address HERE+1
(c) 1997 Microchip Technology Inc.
Preliminary
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PIC16C55X(A)
CLRWDT Syntax: Operands: Operation: Clear Watchdog Timer [ label ] CLRWDT None 00h WDT 0 WDT prescaler, 1 TO 1 PD TO, PD
00 0000 0110 0100 CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
DECF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Decrement f [ label ] DECF f,d 0 f 127 d [0,1] (f) - 1 (dest) Z
00 0011 dfff ffff Decrement register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
Status Affected: Encoding: Description:
Words: Cycles: Example
1 1
DECF CNT, 1 CNT Z = = = = 0x01 0 0x00 1
Words: Cycles: Example
1 1
CLRWDT
Before Instruction
Before Instruction
WDT counter = ? 0x00 0 1 1
After Instruction
CNT Z
After Instruction
WDT counter = WDT prescaler= TO = PD =
COMF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Complement f [ label ] COMF 0 f 127 d [0,1] (f) (dest) Z
00 1001 dfff ffff The contents of register 'f' are complemented. If 'd' is 0 the result is stored in W. If 'd' is 1 the result is stored back in register 'f'.
DECFSZ f,d Syntax: Operands: Operation: Status Affected: Encoding: Description:
Decrement f, Skip if 0 [ label ] DECFSZ f,d 0 f 127 d [0,1] (f) - 1 (dest); None
00 1011 dfff ffff
The contents of register 'f' are decremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. If the result is 0, the next instruction, which is already fetched, is discarded. A NOP is executed instead making it a two-cycle instruction.
skip if result = 0
Words: Cycles: Example
1 1
COMF REG1,0 REG1 = = = 0x13 0x13 0xEC
Words: Cycles: Example
1 1(2)
DECFSZ GOTO CONTINUE * * * HERE CNT, 1 LOOP
Before Instruction After Instruction
REG1 W
Before Instruction
PC =
address HERE CNT - 1 0, address CONTINUE 0, address HERE+1
After Instruction
CNT if CNT PC if CNT PC = = = =
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PIC16C55X(A)
GOTO Syntax: Operands: Operation: Status Affected: Encoding: Description: Unconditional Branch [ label ] GOTO k 0 k 2047 k PC<10:0> PCLATH<4:3> PC<12:11> None
10 1kkk kkkk kkkk GOTO is an unconditional branch. The eleven bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two-cycle instruction.
INCFSZ Syntax: Operands: Operation: Status Affected: Encoding: Description:
Increment f, Skip if 0 [ label ] INCFSZ f,d 0 f 127 d [0,1] (f) + 1 (dest), skip if result = 0 None
00 1111 dfff ffff The contents of register 'f' are incremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. If the result is 0, the next instruction, which is already fetched, is discarded. A NOP is executed instead making it a two-cycle instruction.
Words: Cycles: Example
1 2
GOTO THERE
Words: Cycles:
Address THERE
1 1(2)
HERE INCFSZ GOTO CONTINUE * * * CNT, LOOP 1
After Instruction
PC =
Example
Before Instruction
PC = address HERE CNT + 1 0, address CONTINUE 0, address HERE +1
After Instruction
CNT = if CNT= PC = if CNT PC =
INCF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Increment f [ label ] INCF f,d 0 f 127 d [0,1] (f) + 1 (dest) Z
00 1010 dfff ffff The contents of register 'f' are incremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'.
IORLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Inclusive OR Literal with W [ label ] IORLW k 0 k 255 (W) .OR. k (W) Z
11 1000 kkkk kkkk The contents of the W register is OR'ed with the eight bit literal 'k'. The result is placed in the W register.
Words: Cycles: Example
1 1
IORLW W 0x35 = = = 0x9A 0xBF 1
Words: Cycles: Example
1 1
INCF CNT, 1 CNT Z = = = = 0xFF 0 0x00 1
Before Instruction After Instruction
W Z
Before Instruction
After Instruction
CNT Z
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Preliminary
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PIC16C55X(A)
IORWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Inclusive OR W with f [ label ] IORWF f,d 0 f 127 d [0,1] (W) .OR. (f) (dest) Z
00 0100 dfff ffff Inclusive OR the W register with register 'f'. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'.
MOVF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Move f [ label ] MOVF f,d 0 f 127 d [0,1] (f) (dest) Z
00 1000 dfff ffff The contents of register f is moved to a destination dependant upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag Z is affected.
Words: Cycles: Example
1 1
IORWF RESULT, 0 RESULT = W = 0x13 0x91 0x13 0x93 1
Words: Cycles: Example
1 1
MOVF FSR, 0 W = value in FSR register Z =1
Before Instruction
After Instruction
RESULT = W = Z =
After Instruction
MOVLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Move Literal to W [ label ] k (W) None
11 00xx kkkk kkkk The eight bit literal 'k' is loaded into W register. The don't cares will assemble as 0's.
MOVWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example
Move W to f [ label ] (W) (f) None
00 0000 1fff ffff Move data from W register to register 'f'.
MOVLW k
MOVWF
f
0 k 255
0 f 127
1 1
MOVWF OPTION OPTION = W = 0xFF 0x4F 0x4F 0x4F
Words: Cycles: Example
1 1
MOVLW W 0x5A = 0x5A
Before Instruction
After Instruction
After Instruction
OPTION = W =
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PIC16C55X(A)
NOP Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1
NOP
No Operation [ label ] None No operation None
00 0000 0xx0 0000
RETFIE Syntax: Operands: Operation: Status Affected: Encoding: Description:
Return from Interrupt [ label ] None TOS PC, 1 GIE None
00 0000 0000 1001 Return from Interrupt. Stack is POPed and Top of Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction.
NOP
RETFIE
No operation.
Words: Cycles: Example
1 2
RETFIE
After Interrupt
PC = GIE = TOS 1
OPTION Syntax: Operands: Operation: Encoding: Description:
Load Option Register [ label ] None (W) OPTION
00 0000 0110 0010
RETLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Return with Literal in W [ label ] RETLW k 0 k 255 k (W); TOS PC None
11 01xx kkkk kkkk The W register is loaded with the eight bit literal 'k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction.
OPTION
Status Affected: None
The contents of the W register are loaded in the OPTION register. This instruction is supported for code compatibility with PIC16C5X products. Since OPTION is a readable/writable register, the user can directly address it.
Words: Cycles: Example
1 1
To maintain upward compatibility with future PICmicroTM products, do not use this instruction.
Words: Cycles: Example
1 2
CALL TABLE * value * TABLE * ADDWF RETLW RETLW * * * RETLW ;W contains table ;offset value ;W now has table
PC k1 k2
;W = offset ;Begin table ;
kn
; End of table
Before Instruction
W W = = 0x07 value of k8
After Instruction
(c) 1997 Microchip Technology Inc.
Preliminary
DS40143B-page 59
PIC16C55X(A)
RETURN Syntax: Operands: Operation: Status Affected: Encoding: Description: Return from Subroutine [ label ] None TOS PC None
00 0000 0000 1000 Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two cycle instruction.
RRF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Rotate Right f through Carry [ label ] RRF f,d 0 f 127 d [0,1] See description below C
00 1100 dfff ffff The contents of register 'f' are rotated one bit to the right through the Carry Flag. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. C Register f
RETURN
Words: Cycles: Example
1 2
RETURN
After Interrupt
PC = TOS
Words: Cycles: Example
1 1
RRF REG1 C REG1,0 = = = = = 1110 0110 0 1110 0110 0111 0011 0
Before Instruction
After Instruction
REG1 W C
RLF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Rotate Left f through Carry [ label ] 0 f 127 d [0,1] See description below C
00 1101 dfff ffff The contents of register 'f' are rotated one bit to the left through the Carry Flag. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is stored back in register 'f'. C Register f
SLEEP Syntax: Operands: Operation: [ label ] None 00h WDT, 0 WDT prescaler, 1 TO, 0 PD TO, PD
00 0000 0110 0011 The power-down status bit, PD is cleared. Time-out status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into SLEEP mode with the oscillator stopped. See Section 7.8 for more details.
RLF
f,d
SLEEP
Status Affected: Encoding: Description:
Words: Cycles: Example
1 1
RLF REG1,0 REG1 C = = = = = 1110 0110 0 1110 0110 1100 1100 1
Words: Cycles: Example:
1 1 SLEEP
Before Instruction
After Instruction
REG1 W C
DS40143B-page 60
Preliminary
(c) 1997 Microchip Technology Inc.
PIC16C55X(A)
SUBLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Subtract W from Literal [ label ] SUBLW k 0 k 255 k - (W) (W) C, DC, Z 11 110x kkkk kkkk Operation: Status Affected: Encoding: Description: SUBWF Syntax: Operands: Subtract W from f [ label ] 0 f 127 d [0,1] (f) - (W) (dest) C, DC, Z 00 0010 dfff ffff SUBWF f,d
The W register is subtracted (2's complement method) from the eight bit literal 'k'. The result is placed in the W register.
Words: Cycles: Example 1:
1 1 SUBLW 0x02
W C = = 1 ?
Subtract (2's complement method) W register from register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
Words: Cycles: Example 1:
1 1 SUBWF
REG1 W C
Before Instruction
REG1,1
= = = 3 2 ?
Before Instruction
After Instruction
W= C = tive 1 1; result is posi-
After Instruction
REG1 W C = = = 1 2 1; result is positive
Example 2:
Before Instruction
W C = = 2 ?
After Instruction
W C = = 0 1; result is zero
Example 2:
Before Instruction
REG1 W C = = = 2 2 ?
Example 3:
Before Instruction
W C = = 3 ?
After Instruction
REG1 W C = = = 0 2 1; result is zero
After Instruction
W= C = tive 0xFF 0; result is nega-
Example 3:
Before Instruction
REG1 W C = = = 1 2 ?
After Instruction
REG1 W C = = = 0xFF 2 0; result is negative
(c) 1997 Microchip Technology Inc.
Preliminary
DS40143B-page 61
PIC16C55X(A)
SWAPF Syntax: Operands: Operation: Status Affected: Encoding: Description: Swap Nibbles in f [ label ] SWAPF f,d 0 f 127 d [0,1] (f<3:0>) (dest<7:4>), (f<7:4>) (dest<3:0>) None
00
XORLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Exclusive OR Literal with W [ label ] XORLW k 0 k 255 (W) .XOR. k (W) Z 11 1010 kkkk kkkk
The contents of the W register are XOR'ed with the eight bit literal 'k'. The result is placed in the W register.
1110
dfff
ffff
The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0 the result is placed in W register. If 'd' is 1 the result is placed in register 'f'.
Words: Cycles: Example:
1 1 XORLW 0xAF
W = 0xB5
Words: Cycles: Example
1 1
SWAPF REG, 0
Before Instruction After Instruction
W = = 0xA5 0x5A = 0x1A
Before Instruction
REG1 = 0xA5
After Instruction
REG1 W
TRIS Syntax: Operands: Operation: Encoding: Description:
Load TRIS Register [ label ] TRIS 5f7 (W) TRIS register f; f
XORWF Syntax: Operands: Operation:
Exclusive OR W with f [ label ] XORWF 0 f 127 d [0,1] (W) .XOR. (f) (dest) Z
00 0110 dfff ffff Exclusive OR the contents of the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
f,d
Status Affected: None
00
0000
0110
0fff
Status Affected: Encoding: Description:
The instruction is supported for code compatibility with the PIC16C5X products. Since TRIS registers are readable and writable, the user can directly address them.
Words: Cycles: Example
1 1
To maintain upward compatibility with future PICmicroTM products, do not use this instruction.
Words: Cycles: Example
1 1 XORWF
REG 1
Before Instruction
REG W = = 0xAF 0xB5
After Instruction
REG W = = 0x1A 0xB5
DS40143B-page 62
Preliminary
(c) 1997 Microchip Technology Inc.
PIC16C55X(A)
9.0
9.1
DEVELOPMENT SUPPORT
Development Tools
9.3
ICEPIC: Low-Cost PICmicroTM In-Circuit Emulator
The PICmicrTM microcontrollers are supported with a full range of hardware and software development tools: * PICMASTER/DS40143BICMASTER CE Real-Time In-Circuit Emulator * ICEPIC Low-Cost PIC16C5X and PIC16CXXX In-Circuit Emulator * PRO MATE(R) II Universal Programmer * PICSTART(R) Plus Entry-Level Prototype Programmer * PICDEM-1 Low-Cost Demonstration Board * PICDEM-2 Low-Cost Demonstration Board * PICDEM-3 Low-Cost Demonstration Board * MPASM Assembler * MPLABTM SIM Software Simulator * MPLAB-C (C Compiler) * Fuzzy Logic Development System (fuzzyTECH(R)-MP)
ICEPIC is a low-cost in-circuit emulator solution for the Microchip PIC12CXXX, PIC16C5X and PIC16CXXX families of 8-bit OTP microcontrollers. ICEPIC is designed to operate on PC-compatible machines ranging from 286-AT(R) through PentiumTM based machines under Windows 3.x environment. ICEPIC features real time, non-intrusive emulation.
9.4
PRO MATE II: Universal Programmer
The PRO MATE II Universal Programmer is a full-featured programmer capable of operating in stand-alone mode as well as PC-hosted mode. The PRO MATE II has programmable VDD and VPP supplies which allows it to verify programmed memory at VDD min and VDD max for maximum reliability. It has an LCD display for displaying error messages, keys to enter commands and a modular detachable socket assembly to support various package types. In standalone mode the PRO MATE II can read, verify or program PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX devices. It can also set configuration and code-protect bits in this mode.
9.2
PICMASTER: High Performance Universal In-Circuit Emulator with MPLAB IDE
The PICMASTER Universal In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for all microcontrollers in the SX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX families. PICMASTER is supplied with the MPLABTM Integrated Development Environment (IDE), which allows editing, "make" and download, and source debugging from a single environment. Interchangeable target probes allow the system to be easily reconfigured for emulation of different processors. The universal architecture of the PICMASTER allows expansion to support all new Microchip microcontrollers. The PICMASTER Emulator System has been designed as a real-time emulation system with advanced features that are generally found on more expensive development tools. The PC compatible 386 (and higher) machine platform and Microsoft Windows(R) 3.x environment were chosen to best make these features available to you, the end user. A CE compliant version of PICMASTER is available for European Union (EU) countries.
9.5
PICSTART Plus Entry Level Development System
The PICSTART programmer is an easy-to-use, lowcost prototype programmer. It connects to the PC via one of the COM (RS-232) ports. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. PICSTART Plus is not recommended for production programming. PICSTART Plus supports all PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX devices with up to 40 pins. Larger pin count devices such as the PIC16C923 and PIC16C924 may be supported with an adapter socket.
(c) 1997 Microchip Technology Inc.
DS40143B - page 63
PIC16C55X(A)
9.6 PICDEM-1 Low-Cost PICmicro Demonstration Board
an RS-232 interface, push-button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external LCD module and a keypad. Also provided on the PICDEM-3 board is an LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature and day of the week. The PICDEM-3 provides an additional RS-232 interface and Windows 3.1 software for showing the demultiplexed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals.
The PICDEM-1 is a simple board which demonstrates the capabilities of several of Microchip's microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The users can program the sample microcontrollers provided with the PICDEM-1 board, on a PRO MATE II or PICSTART-Plus programmer, and easily test firmware. The user can also connect the PICDEM-1 board to the PICMASTER emulator and download the firmware to the emulator for testing. Additional prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push-button switches and eight LEDs connected to PORTB.
9.9
MPLABTM Integrated Development Environment Software
The MPLAB IDE Software brings an ease of software development previously unseen in the 8-bit microcontroller market. MPLAB is a windows based application which contains: * A full featured editor * Three operating modes - editor - emulator - simulator * A project manager * Customizable tool bar and key mapping * A status bar with project information * Extensive on-line help MPLAB allows you to: * Edit your source files (either assembly or `C') * One touch assemble (or compile) and download to PICmicro tools (automatically updates all project information) * Debug using: - source files - absolute listing file * Transfer data dynamically via DDE (soon to be replaced by OLE) * Run up to four emulators on the same PC The ability to use MPLAB with Microchip's simulator allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured emulator with minimal retraining due to development tools.
9.7
PICDEM-2 Low-Cost PIC16CXX Demonstration Board
The PICDEM-2 is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-2 board, on a PRO MATE II programmer or PICSTART-Plus, and easily test firmware. The PICMASTER emulator may also be used with the PICDEM-2 board to test firmware. Additional prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push-button switches, a potentiometer for simulated analog input, a Serial EEPROM to demonstrate usage of the I2C bus and separate headers for connection to an LCD module and a keypad.
9.8
PICDEM-3 Low-Cost PIC16CXXX Demonstration Board
The PICDEM-3 is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with a LCD Module. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-3 board, on a PRO MATE II programmer or PICSTART Plus with an adapter socket, and easily test firmware. The PICMASTER emulator may also be used with the PICDEM-3 board to test firmware. Additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). Some of the features include
9.10
Assembler (MPASM)
The MPASM Universal Macro Assembler is a PChosted symbolic assembler. It supports all microcontroller series including the PIC12C5XX, PIC14000, PIC16C5X, PIC16CXXX, and PIC17CXX families. MPASM offers full featured Macro capabilities, conditional assembly, and several source and listing formats. It generates various object code formats to support Microchip's development tools as well as third party programmers. MPASM allows full symbolic debugging from PICMASTER, Microchip's Universal Emulator System.
DS40143B - page 64
(c) 1997 Microchip Technology Inc.
PIC16C55X(A)
MPASM has the following features to assist in developing software for specific use applications. * Provides translation of Assembler source code to object code for all Microchip microcontrollers. * Macro assembly capability. * Produces all the files (Object, Listing, Symbol, and special) required for symbolic debug with Microchip's emulator systems. * Supports Hex (default), Decimal and Octal source and listing formats. MPASM provides a rich directive language to support programming of the PICmicro. Directives are helpful in making the development of your assemble source code shorter and more maintainable.
9.14
MP-DriveWayTM - Application Code Generator
MP-DriveWay is an easy-to-use Windows-based Application Code Generator. With MP-DriveWay you can visually configure all the peripherals in a PICmicro device and, with a click of the mouse, generate all the initialization and many functional code modules in C language. The output is fully compatible with Microchip's MPLAB-C C compiler. The code produced is highly modular and allows easy integration of your own code. MP-DriveWay is intelligent enough to maintain your code through subsequent code generation.
9.15
SEEVAL(R) Evaluation and Programming System
9.11
Software Simulator (MPLAB-SIM)
The MPLAB-SIM Software Simulator allows code development in a PC host environment. It allows the user to simulate the PICmicro series microcontrollers on an instruction level. On any given instruction, the user may examine or modify any of the data areas or provide external stimulus to any of the pins. The input/ output radix can be set by the user and the execution can be performed in; single step, execute until break, or in a trace mode. MPLAB-SIM fully supports symbolic debugging using MPLAB-C and MPASM. The Software Simulator offers the low cost flexibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool.
The SEEVAL SEEPROM Designer's Kit supports all Microchip 2-wire and 3-wire Serial EEPROMs. The kit includes everything necessary to read, write, erase or program special features of any Microchip SEEPROM product including Smart SerialsTM and secure serials. The Total EnduranceTM Disk is included to aid in tradeoff analysis and reliability calculations. The total kit can significantly reduce time-to-market and result in an optimized system.
9.16
KEELOQ(R) Evaluation and Programming Tools
9.12
C Compiler (MPLAB-C)
KEELOQ evaluation and programming tools support Microchips HCS Secure Data Products. The HCS evaluation kit includes an LCD display to show changing codes, a decoder to decode transmissions, and a programming interface to program test transmitters.
The MPLAB-C Code Development System is a complete `C' compiler and integrated development environment for Microchip's PICmicroTM family of microcontrollers. The compiler provides powerful integration capabilities and ease of use not found with other compilers. For easier source level debugging, the compiler provides symbol information that is compatible with the MPLAB IDE memory display.
9.13
Fuzzy Logic Development System (fuzzyTECH-MP)
fuzzyTECH-MP fuzzy logic development tool is available in two versions - a low cost introductory version, MP Explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version, fuzzyTECH-MP, edition for implementing more complex systems.
Both versions include Microchip's fuzzyLABTM demonstration board for hands-on experience with fuzzy logic systems implementation.
(c) 1997 Microchip Technology Inc.
DS40143B - page 65
TABLE 9-1:
PIC12C5XX
PIC14000
PIC16C5X
PIC16CXXX
PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X
PIC17C75X
24CXX 25CXX 93CXX
HCS200 HCS300 HCS301
Emulator Products
Software Tools
Programmers
(c) 1997 Microchip Technology Inc.
Demo Boards
DS40143B - page 66
Available 3Q97
PICMASTER(R)/ PICMASTER-CE In-Circuit Emulator
ICEPIC Low-Cost In-Circuit Emulator
PIC16C55X(A)
MPLABTM Integrated Development Environment
MPLABTM C Compiler
fuzzyTECH(R)-MP Explorer/Edition Fuzzy Logic Dev. Tool
MP-DriveWayTM Applications Code Generator
DEVELOPMENT TOOLS FROM MICROCHIP
Total EnduranceTM Software Model
PICSTART(R) Lite Ultra Low-Cost Dev. Kit
PICSTART(R) Plus Low-Cost Universal Dev. Kit
PRO MATE(R) II Universal Programmer
KEELOQ(R) Programmer
SEEVAL(R) Designers Kit
PICDEM-1
PICDEM-2
PICDEM-3
KEELOQ(R) Evaluation Kit
PIC16C55X(A)
10.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings Ambient Temperature under bias ............................................................................................................. -40 to +125C Storage Temperature................................................................................................................................ -65 to +150C Voltage on any pin with respect to VSS (except VDD and MCLR)...................................................... -0.6V to VDD +0.6V Voltage on VDD with respect to VSS ............................................................................................................... 0 to +7.5V Voltage on MCLR with respect to VSS (Note 2)................................................................................................. 0 to +14V Total power Dissipation (Note 1) ...............................................................................................................................1.0W Maximum Current out of VSS pin...........................................................................................................................300 mA Maximum Current into VDD pin..............................................................................................................................250 mA Input Clamp Current, IIK (VI<0 or VI> VDD) ...................................................................................................................... 20 mA Output Clamp Current, IOK (V0 <0 or V0>VDD) ............................................................................................................... 20 mA Maximum Output Current sunk by any I/O pin ........................................................................................................25 mA Maximum Output Current sourced by any I/O pin ...................................................................................................25 mA Maximum Current sunk by PORTA and PORTB ...................................................................................................200 mA Maximum Current sourced by PORTA and PORTB ..............................................................................................200 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOl x IOL) NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
(c) 1997 Microchip Technology Inc.
Preliminary
DS40143B-page 67
PIC16C55X(A)
TABLE 10-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
PIC16C55XA-04 VDD: 3.0V to 5.5V IDD: 3.3 mA max.@5.5V IPD: 20 A max. @4.0V Freq: 4.0 MHz max. VDD: 3.0V to 5.5V IDD: 3.3 mA max.@5.5V IPD: 20 A max. @4.0V Freq: 4.0 MHz max. VDD: 4.5V to 5.5V IDD: 9.0 mA typ. @5.5V IPD: 1.0 A typ. @4.0V Freq: 4.0 MHz max. VDD: 3.0V to 5.5V IDD: 35 A typ. @32 kHz, 3.0V IPD: 1.0 A typ. @4.0 V Freq: 200 kHz maxi. PIC16C55X-20 VDD: 4.5V to 5.5V IDD: 1.8 mA typ. @5.5V IPD: 1.0 A typ. @4.5V Freq: 4.0 MHz max. PIC16C55XA-20 VDD: 4.5V to 5.5V IDD: 1.8 mA typ. @5.5V IPD: 1.0 A typ. @4.5V Freq: 4.0 MHz max. PIC16LC55X-04 VDD: 2.5V to 5.5V IDD: 1.4 mA typ. @3.0V IPD: 0.7 A typ. @3.0V Freq: 4.0 MHz max. PIC16C55X JW Devices VDD: 3.0V to 5.5V IDD: 3.3 mA max. @5.5V IPD: 20 A max. @4.0V Freq: 4.0 MHz max. PIC16C55XA JW Devices VDD: 3.0V to 5.5V IDD: 3.3 mA max. @5.5V IPD: 20 A max. @4.0V Freq: 4.0 MHz max.
OSC RC
PIC16C55X-04 VDD: 3.0V to 5.5V IDD: 3.3 mA max.@5.5V IPD: 20 A max. @4.0V Freq: 4.0 MHz max. VDD: 3.0V to 5.5V IDD: 3.3 mA max.@5.5V IPD: 20 A max. @4.0V Freq: 4.0 MHz max. VDD: 4.5V to 5.5V IDD: 9.0 mA typ. @5.5V IPD: 1.0 A typ. @4.0V Freq: 4.0 MHz max. VDD: 3.0V to 5.5V IDD: 35 A typ. @32 kHz, 3.0V IPD: 1.0 A typ. @4.0 V Freq: 200 kHz maxi.
XT
VDD: 4.5V to 5.5V IDD: 1.8 mA typ. @5.5V IPD: 1.0 A typ. @4.5V Freq: 4.0 MHz max.
VDD: 4.5V to 5.5V IDD: 1.8 mA typ. @5.5V IPD: 1.0 A typ. @4.5V Freq: 4.0 MHz max.
VDD: 2.5V to 5.5V IDD: 1.4 mA typ. @3.0V IPD: 0.7 A typ. @3.0V Freq: 4.0 MHz max.
VDD: 3.0V to 5.5V IDD: 3.3 mA max. @5.5V IPD: 20 A max. @4.0V Freq: 4.0 MHz max.
VDD: 3.0V to 5.5V IDD: 3.3 mA max. @5.5V IPD: 20 A max. @4.0V Freq: 4.0 MHz max.
HS
VDD: 4.5V to 5.5V IDD: 20 mA max. @5.5V IPD: 1.0 A typ. @4.5V Freq: 20 MHz max.
VDD: 4.5V to 5.5V IDD: 20 mA max. @5.5V IPD: 1.0 A typ. @4.5V Freq: 20 MHz max.
Do not use in HS mode
VDD: 4.5V to 5.5V IDD: 20 mA max.@5.5V IPD: 1.0 A typ. @4.5V Freq: 20 MHz max. VDD: 2.5V to 5.5V IDD: 32 A max. @32 kHz, 3.0V IPD: 9.0 A max. @3.0V Freq: 200 kHz max.
VDD: 4.5V to 5.5V IDD: 20 mA max.@5.5V IPD: 1.0 A typ. @4.5V Freq: 20 MHz max. VDD: 3.0V to 5.5V IDD: 32 A max. @32 kHz, 3.0V IPD: 9.0 A max.@3.0V Freq: 200 kHz max.
LP
Do not use in LP mode
Do not use in LP mode
VDD: 2.5V to 5.5V IDD: 32 A max. @32 kHz, 3.0V IPD: 9.0 A max. @3.0V Freq: 200 kHz max.
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that guarantees the specifications required.
DS40143B-page 68
Preliminary
(c) 1997 Microchip Technology Inc.
PIC16C55X(A)
(A)
10.1
DC CHARACTERISTICS:
PIC16C55X(A)-04 (Commercial, Industrial, Extended) PIC16C55X(A)-20 (Commercial, Industrial, Extended)
Param No.
Sym
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial and 0C TA +70C for commercial and -40C TA +125C for extended Characteristic Min Typ Max Units Supply Voltage RAM Data Retention Voltage (Note 1) VDD start voltage to ensure Power-on Reset VDD rise rate to ensure Power-on Reset Supply Current (Note 2) 3.0 4.5 - - 0.05* - 1.5* VSS - 1.8 5.5 5.5 - - - 3.3 V V V V
Conditions
D001 VDD D001A D002 VDR D003 D004 D010 VPOR SVDD IDD
XT, RC and LP osc configuration HS osc configuration Device in SLEEP mode
D010A
-
35
70
D013
-
9.0
20
IWDT D020 IPD IWDT * Note 1: 2:
WDT Current (Note 5) Power Down Current (Note 3) WDT Current (Note 5)
- - -
6.0 1.0 6.0
20 25 2.5 15 20
See section on power-on reset for details V/ms See section on power-on reset for details mA XT and RC osc configuration FOSC = 4 MHz, VDD = 5.5V, WDT disabled (Note 4) A LP osc configuration, PIC16C55X-04 only FOSC = 32 kHz, VDD = 4.0V, WDT disabled mA HS osc configuration FOSC = 20 MHz, VDD = 5.5V, WDT disabled A VDD = 4.0V A (+85C to +125C) A VDD=4.0V, WDT disabled A (+85C to +125C) A VDD=4.0V (+85C to +125C)
3: 4: 5:
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C, unless otherwise stated. These parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins configured as input, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. The power down current in SLEEP mode does not depend on the oscillator type. Power down current is measured with the part in SLEEP mode, with all I/O pins configured as input and tied to VDD or VSS. For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in k. The current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement.
(c) 1997 Microchip Technology Inc.
Preliminary
DS40143B-page 69
PIC16C55X(A)
10.2 DC CHARACTERISTICS: PIC16LC55X-04 (Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial and 0C TA +70C for commercial and -40C TA +125C for extended Characteristic Min Typ Max Units Supply Voltage RAM Data Retention Voltage (Note 1) VDD start voltage to ensure Power-on Reset VDD rise rate to ensure Power-on Reset Supply Current (Note 2) 3.0 2.5 - - 0.05* - 1.5* VSS - 1.4 5.5 5.5 - - - 2.5 V V V
Param No. D001 D002 D003 D004 D010
Sym VDD VDR VPOR SVDD IDD
Conditions
XT and RC osc configuration LP osc configuration Device in SLEEP mode
D010A
-
26
53
D020 * Note 1: 2:
3: 4: 5:
IWDT WDT Current (Note 5) - 6.0 15 IPD Power Down Current (Note 3) - 0.7 2 IWDT WDT Current (Note 5) - 6.0 15 These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C, unless otherwise stated. These parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1=external square wave, from rail to rail; all I/O pins configured as input, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. The power down current in SLEEP mode does not depend on the oscillator type. Power down current is measured with the part in SLEEP mode, with all I/O pins configured as input and tied to VDD or VSS. For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in k. The current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement.
See section on Power-on Reset for details V/ms See section on Power-on Reset for details mA XT and RC osc configuration FOSC = 2.0 MHz, VDD = 3.0V, WDT disabled (Note 4) A LP osc configuration FOSC = 32 kHz, VDD = 3.0V, WDT disabled A VDD = 3.0V A VDD=3.0V, WDT disabled A VDD=3.0V
DS40143B-page 70
Preliminary
(c) 1997 Microchip Technology Inc.
PIC16C55X(A)
10.3 DC CHARACTERISTICS: PIC16C55X(A) (Commercial, Industrial, Extended) PIC16LC55X (Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial and 0C TA +70C for commercial and -40C TA +125C for automotive Operating voltage VDD range as described in DC spec Table 10-1 Param. Sym No.
VIL
Characteristic Input Low Voltage I/O ports with TTL buffer
Min
Typ
Max
Unit
Conditions
D030 D031 D032
VSS VSS Vss Vss Vss
-
with Schmitt Trigger input MCLR, RA4/T0CKI,OSC1 (in RC mode) D033 OSC1 (in XT* and HS) OSC1 (in LP*) VIH Input High Voltage I/O ports D040 with TTL buffer D041 with Schmitt Trigger input D042 MCLR RA4/T0CKI D043 OSC1 (XT*, HS and LP*) D043A OSC1 (in RC mode) IPURB PORTB weak pull-up current D070 Input Leakage Current IIL (Notes 2, 3) I/O ports (Except PORTA) D060 PORTA D061 RA4/T0CKI D063 OSC1, MCLR
VOL Output Low Voltage
-
0.8V 0.15VDD 0.2VDD 0.2VDD
V VDD = 4.5V to 5.5V otherwise V V Note1
V 0.3VDD 0.6VDD-1.0 V
2.0V 0.8VDD 0.8VDD 0.7VDD 0.9VDD 50 200
VDD VDD VDD VDD 400
V V V Note1 A VDD = 5.0V, VPIN = VSS A A A A VSS VPIN VDD, pin at hi-impedance Vss VPIN VDD, pin at hi-impedance Vss VPIN VDD Vss VPIN VDD, XT, HS and LP osc configuration IOL=8.5 mA, VDD=4.5V, IOL=7.0 mA, VDD=4.5V, IOL=1.6 mA, VDD=4.5V, IOL=1.2 mA, VDD=4.5V, -40 to +85C +125C -40 to +85C +125C
-
-
1.0 0.5 1.0 5.0
D080 D083
I/O ports
D090
OSC2/CLKOUT (RC only) VOH Output High Voltage (Note 3) I/O ports (Except RA4) VDD-0.7 VDD-0.7 OSC2/CLKOUT (RC only) VDD-0.7 VDD-0.7
-
-
0.6 0.6 0.6 0.6 -
V V V V
D092
*
14* These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the PIC16C55X(A) be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as coming out of the pin. *
VOD Open-Drain High Voltage
V IOH=-3.0 mA, VDD=4.5V, -40 to +85C V IOH=-2.5 mA, VDD=4.5V, +125C V IOH=-1.3 mA, VDD=4.5V, -40 to +85C V IOH=-1.0 mA, VDD=4.5V, +125C V RA4 pin
(c) 1997 Microchip Technology Inc.
Preliminary
DS40143B-page 71
PIC16C55X(A)
10.3 DC CHARACTERISTICS: PIC16C55X(A) (Commercial, Industrial, Extended) PIC16LC55X (Commercial, Industrial, Extended) (Cont.)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial and 0C TA +70C for commercial and -40C TA +125C for automotive Operating voltage VDD range as described in DC spec Table 10-1 Param. Sym No. Characteristic Min Typ Max Unit Conditions
D100 D101
Capacitive Loading Specs on Output Pins COSC2 OSC2 pin
Cio
15
All I/O pins/OSC2 (in RC 50 mode) * These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the PIC16C55X(A) be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as coming out of the pin.
pF In XT, HS and LP modes when external clock used to drive OSC1. pF
DS40143B-page 72
Preliminary
(c) 1997 Microchip Technology Inc.
PIC16C55X(A)
10.4 Timing Parameter Symbology
The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase subscripts (pp) and their meanings: pp ck CLKOUT io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low
T
Time
os t0
OSC1 T0CKI
P R V Z
Period Rise Valid Hi-Impedance
FIGURE 10-1: LOAD CONDITIONS
Load condition 1 VDD/2 Load condition 2
RL
Pin VSS RL = 464 CL = 50 pF 15 pF
CL
Pin VSS
CL
for all pins except OSC2 for OSC2 output
(c) 1997 Microchip Technology Inc.
Preliminary
DS40143B-page 73
PIC16C55X(A)
10.5 Timing Diagrams and Specifications FIGURE 10-2: EXTERNAL CLOCK TIMING
Q4 OSC1 1 2 CLKOUT 3 3 4 4 Q1 Q2 Q3 Q4 Q1
TABLE 10-2:
Parameter No.
EXTERNAL CLOCK TIMING REQUIREMENTS
Characteristic External CLKIN Frequency (Note 1) Oscillator Frequency (Note 1) Min DC DC DC DC 0.1 1 DC 250 50 5 250 250 50 5 1.0 100* 2* 20* 25* 50* 15* Typ -- -- -- -- -- -- - -- -- -- -- -- -- -- Fos/4 -- -- -- -- -- -- Max 4 20 200 4 4 20 200 -- -- -- -- 10,000 1,000 -- DC -- -- -- -- -- -- Units Conditions MHz MHz kHz MHz MHz MHz kHz ns ns s ns ns ns s s ns s ns ns ns ns XT and RC osc mode, VDD=5.0V HS osc mode LP osc mode RC osc mode, VDD=5.0V XT osc mode HS osc mode LP osc mode XT and RC osc mode HS osc mode LP osc mode RC osc mode XT osc mode HS osc mode LP osc mode
Sym Fos
1
Tosc
External CLKIN Period (Note 1) Oscillator Period (Note 1)
2 3*
TCY TosL, TosH TosR, TosF
Instruction Cycle Time (Note 1) External Clock in (OSC1) High or Low Time External Clock in (OSC1) Rise or Fall Time
TCY=FOS/4
XT osc mode LP osc mode HS osc mode XT osc mode LP osc mode HS osc mode
4*
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1 pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
*
DS40143B-page 74
Preliminary
(c) 1997 Microchip Technology Inc.
PIC16C55X(A)
FIGURE 10-3: CLKOUT AND I/O TIMING
Q4 OSC1 10 CLKOUT 13 14 I/O Pin (input) 17 I/O Pin (output) old value 20, 21
Note: All tests must be do with specified capacitance loads (Figure 10-1) 50 pF on I/O pins and CLKOUT
Q1
Q2
Q3
11 22 23 19 18 12 16
15 new value
TABLE 10-3:
Parameter # 10* 11* 12* 13* 14* 15* 16* 17* 18* 19* 20* 21* 22* 23
CLKOUT AND I/O TIMING REQUIREMENTS
Sym TosH2ckL TosH2ckH TckR TckF TckL2ioV TioV2ckH TckH2ioI TosH2ioV TosH2ioI TioV2osH TioR TioF Tinp Trbp Characteristic OSC1 to CLKOUT (Note1) OSC1 to CLKOUT (Note1) CLKOUT rise time (Note1) CLKOUT fall time (Note1) CLKOUT to Port out valid (Note1) Port in valid before CLKOUT (Note1) Port in hold after CLKOUT (Note1) OSC1 (Q1 cycle) to Port out valid OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) Port input valid to OSC1 (I/O in setup time) Port output rise time Port output fall time RB0/INT pin high or low time RB<7:4> change interrupt high or low time Min -- -- -- -- -- -- -- -- -- Tosc +200 ns Tosc +400 ns 0 -- -- 100 200 0 -- -- -- -- 25 40 Tcy Typ 75 -- 75 -- 35 -- 35 -- -- -- -- -- 50 -- -- -- 10 -- 10 -- -- -- -- Max 200 400 200 400 100 200 100 200 20 -- -- -- 150 300 -- -- -- 40 80 40 80 -- -- -- Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
* These parameters are characterized but not tested Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC
(c) 1997 Microchip Technology Inc.
Preliminary
DS40143B-page 75
PIC16C55X(A)
FIGURE 10-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING
VDD MCLR Internal POR 33 PWRT Timeout OSC Timeout Internal RESET Watchdog Timer RESET 34 I/O Pins 32 30
31 34
TABLE 10-4:
Parameter No. 30 31 32 33 34
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS
Sym TmcL Twdt Tost Tpwrt TIOZ Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Prescaler) Oscillation Start-up Timer Period Power-up Timer Period I/O hi-impedance from MCLR low Min 2000 7* -- 28* Typ -- 18 1024 TOSC 72 -- Max -- 33* -- 132* 2.0 Units ns ms -- ms s Conditions -40 to +85C
VDD = 5.0V, -40 to +85C
TOSC = OSC1 period
VDD = 5.0V, -40 to +85C
*
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS40143B-page 76
Preliminary
(c) 1997 Microchip Technology Inc.
PIC16C55X(A)
FIGURE 10-5: TIMER0 CLOCK TIMING
RA4/T0CKI
40 42
41
TMR0
TABLE 10-5:
Parameter No. 40
TIMER0 CLOCK REQUIREMENTS
Min No Prescaler With Prescaler 0.5 TCY + 20* 10* 0.5 TCY + 20* 10* TCY + 40* N Typ -- -- -- -- -- Max -- -- -- -- -- Units Conditions ns ns ns ns ns N = prescale value (1, 2, 4, ..., 256)
Sym Characteristic Tt0H T0CKI High Pulse Width
41
Tt0L T0CKI Low Pulse Width
No Prescaler With Prescaler
42
Tt0P T0CKI Period
*
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
FIGURE 10-6: LOAD CONDITIONS
Load condition 1 VDD/2 Load condition 2
RL
Pin VSS RL = 464 CL = 50 pF 15 pF
CL
Pin VSS
CL
for all pins except OSC2 for OSC2 output
(c) 1997 Microchip Technology Inc.
Preliminary
DS40143B-page 77
PIC16C55X(A)
NOTES:
DS40143B-page 78
Preliminary
(c) 1997 Microchip Technology Inc.
PIC16C55X(A)
11.0 PACKAGING INFORMATION
Symbol List for Ceramic CERDIP Dual In-Line Package Parameters Symbol A A1 A2 A3 B B1 C D D1 E E1 eA eB e1 L N S S1 Notes: 1. 2. 3. 4. Controlling parameter: inches. Parameter "e1" ("e") is non-cumulative. Seating plane (standoff) is defined by board hole size. Parameter "B1" is nominal. Description of Parameters Angular spacing between min. and max. lead positions measured at the gauge plane Distance between seating plane to highest point of body (lid) Distance between seating plane and base plane Distance from base plane to highest point of body (lid) Base body thickness Width of terminal leads Width of terminal lead shoulder which locate seating plane (standoff geometry optional) Thickness of terminal leads Largest overall package parameter of length Body width parameters not including leads Largest overall package width parameter outside of lead Body width parameter - end lead center to end lead center Linear spacing of true minimum lead position center line to center line Linear spacing between true lead position outside of lead to outside of lead Linear spacing between center lines of body standoffs (terminal leads) Distance from seating plane to end of lead Total number of potentially usable lead positions Distance from true position center line of Number 1 lead to the extremity of the body Distance from other end lead edge positions to the extremity of the body
Ceramic CERDIP Dual In-Line Family
(c) 1997 Microchip Technology Inc.
Preliminary
DS40143B-page 79
PIC16C55X(A)
11.1 18-Lead Ceramic CERDIP Dual In-line with Window (300 mil)
N E1 E Pin No. 1 Indicator Area eA eB C
D S Base Plane Seating Plane B1 B D1 e1 L A1 A3 A A2 S1
Package Group: Ceramic CERDIP Dual In-Line (CDP) Millimeters Symbol A A1 A2 A3 B B1 C D D1 E E1 e1 eA eB L N S S1 Min 0 -- 0.381 3.810 3.810 0.355 1.270 0.203 22.352 20.320 7.620 5.588 2.540 7.366 7.620 3.175 18 0.508 0.381 Max 10 5.080 1.7780 4.699 4.445 0.585 1.651 0.381 23.622 20.320 8.382 7.874 2.540 8.128 10.160 3.810 18 1.397 1.270 Notes Min 0 -- 0.015 0.150 0.150 0.014 0.050 0.008 0.880 0.800 0.300 0.220 0.100 0.290 0.300 0.125 18 0.020 0.015 Inches Max 10 0.200 0.070 0.185 0.175 0.023 0.065 0.015 0.930 0.800 0.330 0.310 0.100 0.320 0.400 0.150 18 0.055 0.050 Notes
Typical Typical Reference
Typical Typical Reference
Reference Typical
Reference Typical
DS40143B-page 80
Preliminary
(c) 1997 Microchip Technology Inc.
PIC16C55X(A)
Plastic Dual In-Line Family
Symbol List for Plastic In-Line Package Parameters Symbol A A1 A2 B B1 C D D1 E E1 eA eB e1 L N S S1 Notes: 1. 2. 3. 4. 5. 6. Controlling parameter: inches. Parameter "e1" ("e") is non-cumulative. Seating plane (standoff) is defined by board hole size. Parameter "B1" is nominal. Details of pin Number 1 identifier are optional. Parameters "D + E1" do not include mold flash/protrusions. Mold flash or protrusions shall not exceed .010 inches. Description of Parameters Angular spacing between min. and max. lead positions measured at the gauge plane Distance between seating plane to highest point of body Distance between seating plane and base plane Base body thickness Width of terminal leads Width of terminal lead shoulder which locate seating plane (standoff geometry optional) Thickness of terminal leads Largest overall package parameter of length Body length parameter - end lead center to end lead center Largest overall package width parameter outside of lead Body width parameters not including leads Linear spacing of true minimum lead position center line to center line Linear spacing between true lead position outside of lead to outside of lead Linear spacing between center lines of body standoffs (terminal leads) Distance from seating plane to end of lead Total number of potentially usable lead positions Distance from true position center line of Number 1 lead to the extremity of the body Distance from other end lead edge positions to the extremity of the body
(c) 1997 Microchip Technology Inc.
Preliminary
DS40143B-page 81
PIC16C55X(A)
11.2 18-Lead Plastic Dual In-line (300 mil)
N C E1 E Pin No. 1 Indicator Area eA eB
D S Base Plane Seating Plane B1 B D1 e1 L A1 A2 A S1
Package Group: Plastic Dual In-Line (PLA) Millimeters Symbol A A1 A2 B B1 C D D1 E E1 e1 eA eB L N S S1 Min - 0.381 3.048 0.355 1.524 0.203 22.479 20.320 7.620 6.096 2.489 7.620 8.128 3.048 18 0.889 0.127 Max 4.064 - 3.810 0.559 1.524 0.381 23.495 20.320 8.255 7.112 2.591 7.620 9.906 3.556 18 - - Notes Min - 0.015 0.120 0.014 0.060 0.008 0.885 0.800 0.300 0.240 0.098 0.300 0.320 0.120 18 0.035 0.005 Inches Max 0.160 - 0.150 0.022 0.060 0.015 0.925 0.800 0.325 0.280 0.102 0.300 0.390 0.140 18 - - Notes
Reference Typical Reference
Reference Typical Reference
Typical Reference
Typical Reference
DS40143B-page 82
Preliminary
(c) 1997 Microchip Technology Inc.
PIC16C55X(A)
Plastic Small Outline Family
Symbol List for Small Outline Package Parameters Symbol A A1 B C D E e H L N CP Notes: 1. 2. 3. 4. 5. Controlling parameter: inches. All packages are gull wing lead form. "D" and "E" are reference datums and do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .006 package ends and .010 on sides. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the cross-hatched area to indicate pin 1 position. Terminal numbers are shown for reference. Description of Parameters Angular spacing between min. and max. lead positions measured at the gauge plane Distance between seating plane to highest point of body Distance between seating plane and base plane Width of terminals Thickness of terminals Largest overall package parameter of length Largest overall package width parameter not including leads Linear spacing of true minimum lead position center line to center line Largest overall package dimension of width Length of terminal for soldering to a substrate Total number of potentially usable lead positions Seating plane coplanarity
(c) 1997 Microchip Technology Inc.
Preliminary
DS40143B-page 83
PIC16C55X(A)
11.3 18-Lead Plastic Surface Mount (SOIC - Wide, 300 mil Body)
e B N Index Area E Chamfer h x 45 1 2 3 H L C h x 45
D
Seating Plane
CP
Base Plane
A1
A
Package Group: Plastic SOIC (SO) Millimeters Symbol A A1 B C D E e H h L N CP Min 0 2.362 0.101 0.355 0.241 11.353 7.416 1.270 10.007 0.381 0.406 18 - Max 8 2.642 0.300 0.483 0.318 11.735 7.595 1.270 10.643 0.762 1.143 18 0.102 Notes Min 0 0.093 0.004 0.014 0.009 0.447 0.292 0.050 0.394 0.015 0.016 18 - Inches Max 8 0.104 0.012 0.019 0.013 0.462 0.299 0.050 0.419 0.030 0.045 18 0.004 Notes
Reference
Reference
DS40143B-page 84
Preliminary
(c) 1997 Microchip Technology Inc.
PIC16C55X(A)
11.4 20-Lead Plastic Surface Mount (SSOP - 209 mil Body 5.30 mm)
N Index area
E
H L C
123 e B
A CP
Base plane
Seating plane D A1
Package Group: Plastic SSOP Millimeters Symbol A A1 B C D E e H L N CP Min 0 1.730 0.050 0.250 0.130 7.070 5.200 0.650 7.650 0.550 20 Max 8 1.990 0.210 0.380 0.220 7.330 5.380 0.650 7.900 0.950 20 0.102 Notes Min 0 0.068 0.002 0.010 0.005 0.278 0.205 0.026 0.301 0.022 20 Inches Max 8 0.078 0.008 0.015 0.009 0.289 0.212 0.026 0.311 0.037 20 0.004 Notes
Reference
Reference
(c) 1997 Microchip Technology Inc.
Preliminary
DS40143B-page 85
PIC16C55X(A)
11.5 Package Marking Information 18-Lead PDIP XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX AABBCDE 18-Lead SOIC (.300") XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX AABBCDE 18-Lead CERDIP Windowed XXXXXXXX XXXXXXXX AABBCDE 20-Lead SSOP XXXXXXXXXX XXXXXXXXXX AABBCDE
Legend: MM...M XX...X AA BB C D E
Example PIC16C558A -04I / P456 9523 CBA Example PIC16C558 -04I / S0218 9518 CDK Example 16C558 /JW 9501 CBA Example PIC16C558A -04I / 218 9551 CBP
Microchip part number information Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Facility code of the plant at which wafer is manufactured C = Chandler, Arizona, U.S.A. Mask revision number Assembly code of the plant or country of origin in which part was assembled
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information.
*
Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
DS40143B-page 86
Preliminary
(c) 1997 Microchip Technology Inc.
PIC16C55X(A)
APPENDIX A: ENHANCEMENTS
The following are the list of enhancements over the PIC16C5X microcontroller family: 1. Instruction word length is increased to 14 bits. This allows larger page sizes both in program memory (4K now as opposed to 512 before) and register file (up to 128 bytes now versus 32 bytes before). A PC high latch register (PCLATH) is added to handle program memory paging. PA2, PA1, PA0 bits are removed from STATUS register. Data memory paging is slightly redefined. STATUS register is modified. Four new instructions have been added: RETURN, RETFIE, ADDLW, and SUBLW. Two instructions TRIS and OPTION are being phased out although they are kept for compatibility with PIC16C5X. OPTION and TRIS registers are made addressable. Interrupt capability is added. Interrupt vector is at 0004h. Stack size is increased to 8 deep. Reset vector is changed to 0000h. Reset of all registers is revised. Three different reset (and wake-up) types are recognized. Registers are reset differently. Wake up from SLEEP through interrupt is added. Two separate timers, Oscillator Start-up Timer (OST) and Power-up Timer (PWRT) are included for more reliable power-up. These timers are invoked selectively to avoid unnecessary delays on power-up and wake-up. PORTB has weak pull-ups and interrupt on change feature. Timer0 clock input, T0CKI pin is also a port pin (RA4/T0CKI) and has a TRIS bit. FSR is made a full 8-bit register. "In-circuit programming" is made possible. The user can program PIC16C55X devices using only five pins: VDD, VSS, VPP, RB6 (clock) and RB7 (data in/out). PCON status register is added with a Power-on-Reset (POR) status bit. Code protection scheme is enhanced such that portions of the program memory can be protected, while the remainder is unprotected. PORTA inputs are now Schmitt Trigger inputs.
APPENDIX B: COMPATIBILITY
To convert code written for PIC16C5X to PIC16C55X(A), the user should take the following steps: 1. 2. Remove any program memory page select operations (PA2, PA1, PA0 bits) for CALL, GOTO. Revisit any computed jump operations (write to PC or add to PC, etc.) to make sure page bits are set properly under the new scheme. Eliminate any data memory page switching. Redefine data variables to reallocate them. Verify all writes to STATUS, OPTION, and FSR registers since these have changed. Change reset vector to 0000h.
2.
3. 4. 5.
3. 4.
5. 6. 7. 8. 9.
10. 11.
12. 13. 14. 15.
16. 17.
18.
(c) 1997 Microchip Technology Inc.
Preliminary
DS40143B-page 87
PIC16C55X(A)
NOTES:
DS40143B-page 88
Preliminary
(c) 1997 Microchip Technology Inc.
PIC16C55X(A)
INDEX A
ADDLW Instruction ............................................................. 53 ADDWF Instruction ............................................................. 53 ANDLW Instruction ............................................................. 53 ANDWF Instruction ............................................................. 53 Architectural Overview .......................................................... 9 Assembler MPASM Assembler..................................................... 64 COMF ......................................................................... 56 DECF.......................................................................... 56 DECFSZ ..................................................................... 56 GOTO ......................................................................... 57 INCF ........................................................................... 57 INCFSZ....................................................................... 57 IORLW........................................................................ 57 IORWF........................................................................ 58 MOVF ......................................................................... 58 MOVLW ...................................................................... 58 MOVWF...................................................................... 58 NOP............................................................................ 59 OPTION...................................................................... 59 RETFIE....................................................................... 59 RETLW ....................................................................... 59 RETURN..................................................................... 60 RLF............................................................................. 60 RRF ............................................................................ 60 SLEEP ........................................................................ 60 SUBLW....................................................................... 61 SUBWF....................................................................... 61 SWAPF....................................................................... 62 TRIS ........................................................................... 62 XORLW ...................................................................... 62 XORWF ...................................................................... 62 Instruction Set Summary .................................................... 51 INT Interrupt ....................................................................... 46 INTCON Register ............................................................... 19 Interrupts ............................................................................ 45 IORLW Instruction .............................................................. 57 IORWF Instruction .............................................................. 58
B
BCF Instruction ................................................................... 54 Block Diagram TIMER0....................................................................... 29 TMR0/WDT PRESCALER .......................................... 32 BSF Instruction ................................................................... 54 BTFSC Instruction............................................................... 54 BTFSS Instruction............................................................... 55
C
CALL Instruction ................................................................. 55 Clocking Scheme/Instruction Cycle .................................... 12 CLRF Instruction ................................................................. 55 CLRW Instruction................................................................ 55 CLRWDT Instruction ........................................................... 56 Code Protection .................................................................. 50 COMF Instruction................................................................ 56 Configuration Bits................................................................ 36
D
Data Memory Organization ................................................. 14 DECF Instruction................................................................. 56 DECFSZ Instruction ............................................................ 56 Development Support ......................................................... 63 Development Tools ............................................................. 63
K
KeeLoq(R) Evaluation and Programming Tools ................... 65
E
External Crystal Oscillator Circuit ....................................... 38
M
MOVF Instruction................................................................ 58 MOVLW Instruction ............................................................ 58 MOVWF Instruction ............................................................ 58 MP-DriveWayTM - Application Code Generator .................. 65 MPLAB C ............................................................................ 65 MPLAB Integrated Development Environment Software.... 64
F
Fuzzy Logic Dev. System (fuzzyTECH(R)-MP) .................... 65
G
General purpose Register File ............................................ 14 GOTO Instruction................................................................ 57
N
NOP Instruction .................................................................. 59
I
I/O Ports.............................................................................. 23 I/O Programming Considerations........................................ 27 ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator ............ 63 ID Locations ........................................................................ 50 INCF Instruction .................................................................. 57 INCFSZ Instruction ............................................................. 57 In-Circuit Serial Programming............................................. 50 Indirect Addressing, INDF and FSR Registers ................... 22 Instruction Flow/Pipelining .................................................. 12 Instruction Set ADDLW ....................................................................... 53 ADDWF....................................................................... 53 ANDLW ....................................................................... 53 ANDWF....................................................................... 53 BCF............................................................................. 54 BSF ............................................................................. 54 BTFSC ........................................................................ 54 BTFSS ........................................................................ 55 CALL ........................................................................... 55 CLRF........................................................................... 55 CLRW ......................................................................... 55 CLRWDT..................................................................... 56
O
One-Time-Programmable (OTP) Devices .............................7 OPTION Instruction ............................................................ 59 OPTION Register ............................................................... 18 Oscillator Configurations .................................................... 37 Oscillator Start-up Timer (OST) .......................................... 40
P
Package Marking Information ............................................. 86 Packaging Information ........................................................ 79 PCL and PCLATH .............................................................. 21 PCON Register ................................................................... 20 PICDEM-1 Low-Cost PICmicro Demo Board ..................... 64 PICDEM-2 Low-Cost PIC16CXX Demo Board................... 64 PICDEM-3 Low-Cost PIC16CXXX Demo Board ................ 64 PICMASTER(R) In-Circuit Emulator ..................................... 63 PICSTART(R) Plus Entry Level Development System......... 63 Pinout Description .............................................................. 11 Port RB Interrupt................................................................. 46 PORTA ............................................................................... 23 PORTB ............................................................................... 25 Power Control/Status Register (PCON) ............................. 41 Power-Down Mode (SLEEP) .............................................. 49
(c) 1997 Microchip Technology Inc.
Preliminary
DS40143B-page 89
PIC16C55X(A)
Power-On Reset (POR) ...................................................... 40 Power-up Timer (PWRT)..................................................... 40 Prescaler ............................................................................. 32 PRO MATE(R) II Universal Programmer............................... 63 Program Memory Organization ........................................... 13
LIST OF FIGURES
Figure 3-1: Figure 3-2: Figure 4-1: Figure 4-2: Figure 4-3: Figure 4-4: Figure 4-5: Figure 4-6: Figure 4-7: Figure 4-8: Figure 4-9: Figure 4-10: Figure 4-11: Figure 5-1: Figure 5-2: Figure 5-3: Figure 5-4: Figure 5-5: Figure 6-1: Figure 6-2: Figure 6-3: Figure 6-4: Figure 6-5: Figure 6-6: Figure 7-1: Figure 7-2: Figure 7-3: Figure 7-4: Figure 7-5: Figure 7-6: Figure 7-7: Figure 7-8: Figure 7-9: Figure 7-10: Figure 7-11: Figure 7-12: Figure 7-13: Figure 7-14: Figure 7-15: Figure 7-16: Figure 7-17: BlocK Diagram ........................................... 10 Clock/Instruction Cycle ............................... 12 Program Memory Map and Stack for the PIC16C554/PIC6C554(A) .......................... 13 Program Memory Map and Stack for the PIC16C556(A) ............................................ 13 Program Memory Map and Stack for the PIC16C558/PIC16C558(A) ........................ 13 Data Memory Map for the PIC16C554/554(A) ..................................... 15 Data Memory Map for the PIC16C558/558(A) ..................................... 15 STATUS Register (Address 03h or 83h) ................................................. 17 OPTION Register (address 81h) ................ 18 INTCON Register (address 0Bh or 8Bh)........................................................ 19 PCON Register (Address 8Eh)................... 20 Loading Of PC In Different Situations ........ 21 Direct/indirect Addressing PIC16C55X(A)............................................ 22 Block Diagram of PORT pins RA<3:0>................................... 23 Block Diagram of RA4 Pin .......................... 23 Block Diagram of RB7:RB4 Pins ................ 25 Block Diagram of RB3:RB0 Pins ................ 25 Successive I/O Operation........................... 27 TIMER0 Block Diagram .............................. 29 TIMER0 (TMR0) Timing: Internal Clock/No PrescaleR ................................... 29 TIMER0 Timing: Internal Clock/ Prescale 1:2 ............................................... 30 TIMER0 Interrupt Timing ............................ 30 TIMER0 Timing With External Clock .......... 31 Block Diagram of thE Timer0/WDT Prescaler .................................................... 32 Configuration Word .................................... 36 Crystal Operation (or Ceramic Resonator) (HS, XT or LP Osc Configuration) .............. 37 External Clock Input Operation (HS, XT or LP Osc Configuration) .............. 37 External Parallel Resonant Crystal Oscillator Circuit ......................................... 38 External Series Resonant Crystal Oscillator Circuit ......................................... 38 RC Oscillator Mode .................................... 38 Simplified Block Diagram of On-chip Reset Circuit ............................................... 39 Time-out Sequence on Power-up (MCLR not tied to VDD): Case 1 ................. 43 Time-out Sequence on Power-up (MCLR not tied to VDD): Case 2 ................. 43 Time-out Sequence on Power-up (MCLR tied to VDD)..................................... 43 External Power-on Reset Circuit (For Slow VDD Power-up) ........................... 44 Interrupt Logic ............................................ 45 INT Pin Interrupt Timing ............................. 46 Watchdog Timer Block Diagram................. 48 Summary of Watchdog Timer Registers .................................................... 48 Wake-up from Sleep Through Interrupt ...................................................... 49 Typical In-Circuit Serial Programming Connection ................................................. 50
Q
Quick-Turnaround-Production (QTP) Devices ...................... 7
R
RC Oscillator ....................................................................... 38 Reset................................................................................... 39 RETFIE Instruction.............................................................. 59 RETLW Instruction .............................................................. 59 RETURN Instruction............................................................ 60 RLF Instruction.................................................................... 60 RRF Instruction ................................................................... 60
S
SEEVAL(R) Evaluation and Programming System ............... 65 Serialized Quick-Turnaround-Production (SQTP) Devices ... 7 SLEEP Instruction ............................................................... 60 Software Simulator (MPLAB-SIM)....................................... 65 Special Features of the CPU............................................... 35 Special Function Registers ................................................. 16 Stack ................................................................................... 21 Status Register.................................................................... 17 SUBLW Instruction.............................................................. 61 SUBWF Instruction.............................................................. 61 SWAPF Instruction.............................................................. 62
T
Timer0 TIMER0....................................................................... 29 TIMER0 (TMR0) Interrupt ........................................... 29 TIMER0 (TMR0) Module............................................. 29 TMR0 with External Clock........................................... 31 Timer1 Switching Prescaler Assignment................................. 33 Timing Diagrams and Specifications................................... 74 TMR0 Interrupt .................................................................... 46 TRIS Instruction .................................................................. 62 TRISA.................................................................................. 23 TRISB.................................................................................. 25
W
Watchdog Timer (WDT) ...................................................... 47
X
XORLW Instruction ............................................................. 62 XORWF Instruction ............................................................. 62
LIST OF EXAMPLES
Example 3-1: Instruction Pipeline Flow .................... 12 Example 4-1: Ndirect Addressing............................. 22 Example 5-1: Read-Modify-Write Instructions on an I/O Port..................................... 27 Example 6-1: Changing Prescaler (Timer0WDT)................................... 33 Example 6-2: Changing prescaler (WDTTimer0)................................... 33 Example 7-1: Saving the Status and W Registers in RAM ............................................. 47
DS40143B-page 90
Preliminary
(c) 1997 Microchip Technology Inc.
PIC16C55X(A)
Figure 8-1: Figure 10-1: Figure 10-2: Figure 10-3: Figure 10-4: General Format for Instructions .................. 51 Load Conditions.......................................... 73 External Clock Timing................................. 74 CLKOUT and I/O Timing............................. 75 Reset, Watchdog Timer, Oscillator Start-Up Timer and Power-Up Timer Timing ......................................................... 76 TIMER0 Clock Timing................................. 77 Load Conditions.......................................... 77
Figure 10-5: Figure 10-6:
LIST OF TABLES
Table 1-1: Table 3-1: Table 4-1: Table 5-1: Table 5-2: Table 5-3: Table 5-4: Table 6-1: Table 7-1: Table 7-2: Table 7-3: Table 7-4: Table 7-5: Table 7-6: Table 8-1: Table 8-2: Table 9-1: Table 10-1: PIC16C55X(A) Family of Devices.......... 6 PIC16C55X(A) Pinout Description ....... 11 Special Registers for the PIC16C55X(A) ..................................... 16 PORTA Functions ................................ 24 Summary of Registers Associated With PORTA ........................................ 24 PORTB Functions ................................ 26 Summary of Registers Associated with PORTB ......................................... 26 Registers Associated with Timer0........ 33 Capacitor Selection for Ceramic Resonators (Preliminary) ..................... 37 Capacitor Selection for Crystal Oscillator (Preliminary)......................... 37 Time-out in Various Situations ............. 41 StatUs Bits and Their Significance....... 41 Initialization Condition for Special Registers.............................................. 42 Initialization Condition for Registers..... 42 OPCODE Field Descriptions................ 51 PIC16C55X(A) Instruction SeT ............ 52 Development Tools From Microchip .... 66 Cross Reference of Device Specs for Oscillator Configurations and Frequencies of Operation (Commercial Devices).......................... 67 External Clock Timing Requirements....................................... 74 CLKOUT and I/O Timing Requirements....................................... 75 Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Requirements....................................... 76 TIMER0 Clock Requirements .............. 77
Table 10-2: Table 10-3: Table 10-4:
Table 10-5:
(c) 1997 Microchip Technology Inc.
Preliminary
DS40143B-page 91
PIC16C55X(A)
NOTES:
DS40143B-page 92
Preliminary
(c) 1997 Microchip Technology Inc.
PIC16C55X(A)
ON-LINE SUPPORT
Microchip provides two methods of on-line support. These are the Microchip BBS and the Microchip World Wide Web (WWW) site. Use Microchip's Bulletin Board Service (BBS) to get current information and help about Microchip products. Microchip provides the BBS communication channel for you to use in extending your technical staff with microcontroller and memory experts. To provide you with the most responsive service possible, the Microchip systems team monitors the BBS, posts the latest component data and software tool updates, provides technical help and embedded systems insights, and discusses how Microchip products provide project solutions. The web site, like the BBS, is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site. The procedure to connect will vary slightly from country to country. Please check with your local CompuServe agent for details if you have a problem. CompuServe service allow multiple users various baud rates depending on the local point of access. The following connect procedure applies in most locations. 1. Set your modem to 8-bit, No parity, and One stop (8N1). This is not the normal CompuServe setting which is 7E1. 2. Dial your local CompuServe access number. 3. Depress the key and a garbage string will appear because CompuServe is expecting a 7E1 setting. 4. Type +, depress the key and "Host Name:" will appear. 5. Type MCHIPBBS, depress the key and you will be connected to the Microchip BBS. In the United States, to find the CompuServe phone number closest to you, set your modem to 7E1 and dial (800) 848-4480 for 300-2400 baud or (800) 331-7166 for 9600-14400 baud connection. After the system responds with "Host Name:", type NETWORK, depress the key and follow CompuServe's directions. For voice information (or calling from overseas), you may call (614) 723-1550 for your local CompuServe number. Microchip regularly uses the Microchip BBS to distribute technical information, application notes, source code, errata sheets, bug reports, and interim patches for Microchip systems software products. For each SIG, a moderator monitors, scans, and approves or disapproves files submitted to the SIG. No executable files are accepted from the user community in general to limit the spread of computer viruses.
Connecting to the Microchip Internet Web Site
The Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp.mchip.com/biz/mchip The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: * Latest Microchip Press Releases * Technical Support Section with Frequently Asked Questions * Design Tips * Device Errata * Job Postings * Microchip Consultant Program Member Listing * Links to other useful web sites related to Microchip Products
Systems Information and Upgrade Hot Line
The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive any currently available upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-602-786-7302 for the rest of the world.
960513
Connecting to the Microchip BBS
Connect worldwide to the Microchip BBS using either the Internet or the CompuServe(R) communications network.
Internet:
You can telnet or ftp to the Microchip BBS at the address: mchipbbs.microchip.com
Trademarks: The Microchip name, logo, PIC, PICSTART, PICMASTER, PRO MATE and In-Circuit Serial Programming are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. PICmicro, FlexROM, MPLAB, and fuzzyLAB, are trademarks and SQTP is a service mark of Microchip in the U.S.A.
CompuServe Communications Network:
When using the BBS via the Compuserve Network, in most cases, a local call is your only expense. The Microchip BBS connection does not use CompuServe membership services, therefore you do not need CompuServe membership to join Microchip's BBS. There is no charge for connecting to the Microchip BBS.
(c) 1997 Microchip Technology Inc.
fuzzyTECH is a registered trademark of Inform Software Corporation. IBM, IBM PC-AT are registered trademarks of International Business Machines Corp. Pentium is a trademark of Intel Corporation. Windows is a trademark and MS-DOS, Microsoft Windows are registered trademarks of Microsoft Corporation. CompuServe is a registered trademark of CompuServe Incorporated.
All other trademarks mentioned herein are the property of their respective companies.
Preliminary
DS40143B-page 93
PIC16C55X(A)
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: RE: Technical Publications Manager Reader Response Total Pages Sent
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: PIC16C55X(A) Questions: 1. What are the best features of this document? Y N Literature Number: DS40143B FAX: (______) _________ - _________
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefullness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS40143B-page 94
Preliminary
(c) 1997 Microchip Technology Inc.
PIC16C55X(A)
PIC16C55X(A) Product Identification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales offices.
PART NO.
-XX
X /XX XXX
Pattern: Package: 3-Digit Pattern Code for QTP (blank otherwise) P SO SS JW* I E 04 04 20 = = = = = = = = = = PDIP SOIC (Gull Wing, 300 mil body) SSOP (209 mil) Examples: Windowed CERDIP
f)
Temperature Range: Frequency Range: Device:
0C to +70C -40C to +85C -40C to +125C 200kHz (LP osc) 4 MHz (XT and RC osc) 20 MHz (HS osc)
PIC16C554A - 04/P 301 = Commercial temp., PDIP package, 4 MHz, normal VDD limits, QTP pattern #301. g) PIC16LC558- 04I/SO = Industrial temp., SOIC package, 200kHz, extended VDD limits.
PIC16C55X :VDD range 3.0V to 5.5V PIC16C55XT:VDD range 3.0V to 5.5V (Tape and Reel) PIC16C55XA: VDD range 3.0V to 5.5V PIC16C55XAT: VDD range 3.0V to 5.5V (Tape and Reel) PIC16LC55X:VDD range 2.5V to 5.5V PIC16LC55XT:VDD range 2.5V to 5.5V (Tape and Reel)
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type (including LC devices).
Sales and Support
Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office (see below) 2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277 3. The Microchip's Bulletin Board, via your local CompuServe number (CompuServe membership NOT required). Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302.
(c) 1997 Microchip Technology Inc.
Preliminary
DS40143B-page 95
M
WORLDWIDE SALES & SERVICE
AMERICAS
Corporate Office
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Taiwan, R.O.C
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Toronto
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All rights reserved. (c) 1997, Microchip Technology Incorporated, USA. 9/97
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS40143B-page 96
(c) 1997 Microchip Technology Inc.

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